//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Effects/Wipe.cu", 1399785316, 3585
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
	.file	3 "D:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\MediaCore\\GPUFoundation\\API\\Inc\\GPUFoundation/KernelSupport/KernelCore.h", 1399785310, 7840
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .func  (.param .b32 func_retval0) _Z5clampIfET_S0_S0_S0_(
	.param .b32 _Z5clampIfET_S0_S0_S0__param_0,
	.param .b32 _Z5clampIfET_S0_S0_S0__param_1,
	.param .b32 _Z5clampIfET_S0_S0_S0__param_2
)
{
	.reg .f32 	%f<6>;


	ld.param.f32 	%f1, [_Z5clampIfET_S0_S0_S0__param_0];
	ld.param.f32 	%f2, [_Z5clampIfET_S0_S0_S0__param_1];
	ld.param.f32 	%f3, [_Z5clampIfET_S0_S0_S0__param_2];
	.loc 2 2770 10
	max.ftz.f32 	%f4, %f1, %f2;
	.loc 2 2765 10
	min.ftz.f32 	%f5, %f4, %f3;
	st.param.f32	[func_retval0+0], %f5;
	.loc 3 146 39
	ret;
}

.visible .entry WipeKernel(
	.param .u64 WipeKernel_param_0,
	.param .u32 WipeKernel_param_1,
	.param .u64 WipeKernel_param_2,
	.param .u32 WipeKernel_param_3,
	.param .u64 WipeKernel_param_4,
	.param .u32 WipeKernel_param_5,
	.param .u32 WipeKernel_param_6,
	.param .u32 WipeKernel_param_7,
	.param .u32 WipeKernel_param_8,
	.param .u32 WipeKernel_param_9,
	.param .u32 WipeKernel_param_10,
	.param .u32 WipeKernel_param_11,
	.param .u32 WipeKernel_param_12,
	.param .f32 WipeKernel_param_13,
	.param .f32 WipeKernel_param_14,
	.param .f32 WipeKernel_param_15,
	.param .f32 WipeKernel_param_16,
	.param .f32 WipeKernel_param_17,
	.param .f32 WipeKernel_param_18,
	.param .f32 WipeKernel_param_19
)
{
	.reg .pred 	%p<16>;
	.reg .s16 	%rs<37>;
	.reg .s32 	%r<28>;
	.reg .f32 	%f<144>;
	.reg .s64 	%rd<19>;


	ld.param.u64 	%rd8, [WipeKernel_param_0];
	ld.param.u32 	%r8, [WipeKernel_param_1];
	ld.param.u64 	%rd9, [WipeKernel_param_2];
	ld.param.u32 	%r9, [WipeKernel_param_3];
	ld.param.u64 	%rd10, [WipeKernel_param_4];
	ld.param.u32 	%r10, [WipeKernel_param_5];
	ld.param.u32 	%r11, [WipeKernel_param_6];
	ld.param.u32 	%r12, [WipeKernel_param_7];
	ld.param.u32 	%r13, [WipeKernel_param_8];
	ld.param.u32 	%r16, [WipeKernel_param_9];
	ld.param.u32 	%r14, [WipeKernel_param_10];
	ld.param.u32 	%r17, [WipeKernel_param_11];
	ld.param.u32 	%r15, [WipeKernel_param_12];
	ld.param.f32 	%f79, [WipeKernel_param_13];
	ld.param.f32 	%f80, [WipeKernel_param_14];
	ld.param.f32 	%f81, [WipeKernel_param_15];
	ld.param.f32 	%f82, [WipeKernel_param_16];
	ld.param.f32 	%f83, [WipeKernel_param_17];
	ld.param.f32 	%f84, [WipeKernel_param_18];
	ld.param.f32 	%f85, [WipeKernel_param_19];
	cvta.to.global.u64 	%rd1, %rd10;
	cvta.to.global.u64 	%rd2, %rd8;
	cvta.to.global.u64 	%rd3, %rd9;
	.loc 1 28 1
	mov.u32 	%r18, %ntid.x;
	mov.u32 	%r19, %ctaid.x;
	mov.u32 	%r20, %tid.x;
	mad.lo.s32 	%r1, %r18, %r19, %r20;
	add.s32 	%r2, %r1, %r16;
	mov.u32 	%r21, %ntid.y;
	mov.u32 	%r22, %ctaid.y;
	mov.u32 	%r23, %tid.y;
	mad.lo.s32 	%r3, %r21, %r22, %r23;
	add.s32 	%r4, %r3, %r14;
	.loc 1 28 1
	setp.gt.s32	%p1, %r1, -1;
	add.s32 	%r24, %r17, %r16;
	setp.lt.s32	%p2, %r2, %r24;
	and.pred  	%p3, %p1, %p2;
	setp.gt.s32	%p4, %r3, -1;
	and.pred  	%p5, %p3, %p4;
	.loc 1 28 1
	@!%p5 bra 	BB1_22;
	bra.uni 	BB1_1;

BB1_1:
	add.s32 	%r25, %r15, %r14;
	setp.ge.s32	%p6, %r4, %r25;
	@%p6 bra 	BB1_22;

	.loc 1 28 1
	add.s32 	%r5, %r1, %r12;
	cvt.rn.f32.s32	%f86, %r2;
	cvt.rn.f32.s32	%f87, %r4;
	mul.ftz.f32 	%f88, %f87, %f85;
	fma.rn.ftz.f32 	%f89, %f86, %f84, %f88;
	add.ftz.f32 	%f1, %f89, %f82;
	add.ftz.f32 	%f2, %f89, %f83;
	.loc 1 28 1
	setp.ltu.ftz.f32	%p7, %f2, 0f3F800000;
	.loc 1 28 1
	add.s32 	%r6, %r3, %r13;
	.loc 1 28 1
	mad.lo.s32 	%r26, %r6, %r9, %r5;
	mul.wide.s32 	%rd11, %r26, 16;
	add.s64 	%rd4, %rd3, %rd11;
	mul.wide.s32 	%rd12, %r26, 8;
	add.s64 	%rd5, %rd3, %rd12;
	.loc 1 28 1
	@%p7 bra 	BB1_7;

	setp.eq.s32	%p8, %r11, 0;
	.loc 1 28 1
	@%p8 bra 	BB1_5;

	ld.global.v4.f32 	{%f90, %f91, %f92, %f93}, [%rd4];
	mov.f32 	%f127, %f93;
	mov.f32 	%f126, %f92;
	mov.f32 	%f125, %f91;
	mov.f32 	%f124, %f90;
	bra.uni 	BB1_6;

BB1_5:
	.loc 1 28 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd5];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f124, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f125, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f126, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f127, %temp;
	}

BB1_6:
	mov.f32 	%f140, %f124;
	mov.f32 	%f141, %f125;
	mov.f32 	%f142, %f126;
	mov.f32 	%f143, %f127;
	bra.uni 	BB1_19;

BB1_7:
	.loc 1 28 1
	setp.le.ftz.f32	%p9, %f1, 0f00000000;
	setp.le.ftz.f32	%p10, %f2, 0f00000000;
	and.pred  	%p11, %p10, %p9;
	.loc 1 28 1
	mad.lo.s32 	%r27, %r6, %r8, %r5;
	mul.wide.s32 	%rd13, %r27, 16;
	add.s64 	%rd6, %rd2, %rd13;
	mul.wide.s32 	%rd14, %r27, 8;
	add.s64 	%rd7, %rd2, %rd14;
	.loc 1 28 1
	@%p11 bra 	BB1_15;

	setp.eq.s32	%p12, %r11, 0;
	.loc 1 28 1
	@%p12 bra 	BB1_10;

	ld.global.v4.f32 	{%f94, %f95, %f96, %f97}, [%rd6];
	mov.f32 	%f131, %f97;
	mov.f32 	%f130, %f96;
	mov.f32 	%f129, %f95;
	mov.f32 	%f128, %f94;
	bra.uni 	BB1_11;

BB1_10:
	.loc 1 28 1
	ld.global.v4.u16 	{%rs9, %rs10, %rs11, %rs12}, [%rd7];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs9;
	cvt.f32.f16 	%f128, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs10;
	cvt.f32.f16 	%f129, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs11;
	cvt.f32.f16 	%f130, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs12;
	cvt.f32.f16 	%f131, %temp;
	}

BB1_11:
	.loc 1 28 1
	@%p12 bra 	BB1_13;

	ld.global.v4.f32 	{%f98, %f99, %f100, %f101}, [%rd4];
	mov.f32 	%f135, %f101;
	mov.f32 	%f134, %f100;
	mov.f32 	%f133, %f99;
	mov.f32 	%f132, %f98;
	bra.uni 	BB1_14;

BB1_13:
	.loc 1 28 1
	ld.global.v4.u16 	{%rs17, %rs18, %rs19, %rs20}, [%rd5];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs17;
	cvt.f32.f16 	%f132, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs18;
	cvt.f32.f16 	%f133, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs19;
	cvt.f32.f16 	%f134, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs20;
	cvt.f32.f16 	%f135, %temp;
	}

BB1_14:
	mov.f32 	%f102, 0f00000000;
	.loc 2 2770 10
	max.ftz.f32 	%f103, %f1, %f102;
	mov.f32 	%f104, 0f3F800000;
	.loc 2 2765 10
	min.ftz.f32 	%f105, %f103, %f104;
	.loc 1 28 207
	sub.ftz.f32 	%f106, %f79, %f128;
	fma.rn.ftz.f32 	%f107, %f105, %f106, %f128;
	sub.ftz.f32 	%f108, %f80, %f129;
	fma.rn.ftz.f32 	%f109, %f105, %f108, %f129;
	sub.ftz.f32 	%f110, %f81, %f130;
	fma.rn.ftz.f32 	%f111, %f105, %f110, %f130;
	sub.ftz.f32 	%f112, %f104, %f131;
	fma.rn.ftz.f32 	%f113, %f105, %f112, %f131;
	.loc 2 2770 10
	max.ftz.f32 	%f114, %f2, %f102;
	.loc 2 2765 10
	min.ftz.f32 	%f115, %f114, %f104;
	.loc 1 28 206
	sub.ftz.f32 	%f116, %f132, %f107;
	fma.rn.ftz.f32 	%f140, %f115, %f116, %f107;
	sub.ftz.f32 	%f117, %f133, %f109;
	fma.rn.ftz.f32 	%f141, %f115, %f117, %f109;
	sub.ftz.f32 	%f118, %f134, %f111;
	fma.rn.ftz.f32 	%f142, %f115, %f118, %f111;
	sub.ftz.f32 	%f119, %f135, %f113;
	fma.rn.ftz.f32 	%f143, %f115, %f119, %f113;
	bra.uni 	BB1_19;

BB1_15:
	setp.eq.s32	%p14, %r11, 0;
	.loc 1 28 1
	@%p14 bra 	BB1_17;

	ld.global.v4.f32 	{%f120, %f121, %f122, %f123}, [%rd6];
	mov.f32 	%f139, %f123;
	mov.f32 	%f138, %f122;
	mov.f32 	%f137, %f121;
	mov.f32 	%f136, %f120;
	bra.uni 	BB1_18;

BB1_17:
	.loc 1 28 1
	ld.global.v4.u16 	{%rs25, %rs26, %rs27, %rs28}, [%rd7];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs25;
	cvt.f32.f16 	%f136, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs26;
	cvt.f32.f16 	%f137, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs27;
	cvt.f32.f16 	%f138, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs28;
	cvt.f32.f16 	%f139, %temp;
	}

BB1_18:
	mov.f32 	%f140, %f136;
	mov.f32 	%f141, %f137;
	mov.f32 	%f142, %f138;
	mov.f32 	%f143, %f139;

BB1_19:
	.loc 1 28 1
	mad.lo.s32 	%r7, %r4, %r10, %r2;
	.loc 1 28 1
	setp.eq.s32	%p15, %r11, 0;
	@%p15 bra 	BB1_21;

	mul.wide.s32 	%rd15, %r7, 16;
	add.s64 	%rd16, %rd1, %rd15;
	.loc 1 28 1
	st.global.v4.f32 	[%rd16], {%f140, %f141, %f142, %f143};
	bra.uni 	BB1_22;

BB1_21:
	mul.wide.s32 	%rd17, %r7, 8;
	add.s64 	%rd18, %rd1, %rd17;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f140;
	mov.b16 	%rs33, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f141;
	mov.b16 	%rs34, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f142;
	mov.b16 	%rs35, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f143;
	mov.b16 	%rs36, %temp;
}
	.loc 1 28 231
	st.global.v4.u16 	[%rd18], {%rs33, %rs34, %rs35, %rs36};

BB1_22:
	.loc 1 28 2
	ret;
}


