//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/DisplaySurface/Src/TransparencyGrid.cu", 1399785256, 2071
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry TransparencyGridKernel(
	.param .u64 TransparencyGridKernel_param_0,
	.param .u32 TransparencyGridKernel_param_1,
	.param .u32 TransparencyGridKernel_param_2,
	.param .u32 TransparencyGridKernel_param_3,
	.param .u32 TransparencyGridKernel_param_4,
	.param .u32 TransparencyGridKernel_param_5
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<19>;
	.reg .f32 	%f<5>;
	.reg .s64 	%rd<7>;


	ld.param.u64 	%rd2, [TransparencyGridKernel_param_0];
	ld.param.u32 	%r4, [TransparencyGridKernel_param_1];
	ld.param.u32 	%r5, [TransparencyGridKernel_param_2];
	ld.param.u32 	%r7, [TransparencyGridKernel_param_3];
	ld.param.u32 	%r8, [TransparencyGridKernel_param_4];
	ld.param.u32 	%r6, [TransparencyGridKernel_param_5];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 28 1
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r11, %tid.x;
	mad.lo.s32 	%r1, %r9, %r10, %r11;
	mov.u32 	%r12, %ntid.y;
	mov.u32 	%r13, %ctaid.y;
	mov.u32 	%r14, %tid.y;
	mad.lo.s32 	%r2, %r12, %r13, %r14;
	.loc 1 28 1
	setp.lt.s32	%p1, %r1, %r7;
	setp.lt.s32	%p2, %r2, %r8;
	and.pred  	%p3, %p1, %p2;
	.loc 1 28 1
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 28 1
	div.s32 	%r15, %r1, %r6;
	div.s32 	%r16, %r2, %r6;
	add.s32 	%r17, %r16, %r15;
	and.b32  	%r18, %r17, 1;
	setp.eq.b32	%p4, %r18, 1;
	not.pred 	%p5, %p4;
	.loc 1 28 1
	selp.f32	%f3, 0f3F800000, 0f3F4CCCCD, %p5;
	mov.f32 	%f4, 0f3F800000;
	.loc 1 28 1
	mad.lo.s32 	%r3, %r2, %r4, %r1;
	.loc 1 28 1
	setp.eq.s32	%p6, %r5, 0;
	@%p6 bra 	BB0_3;

	mul.wide.s32 	%rd3, %r3, 16;
	add.s64 	%rd4, %rd1, %rd3;
	.loc 1 28 1
	st.global.v4.f32 	[%rd4], {%f3, %f3, %f3, %f4};
	bra.uni 	BB0_4;

BB0_3:
	mul.wide.s32 	%rd5, %r3, 8;
	add.s64 	%rd6, %rd1, %rd5;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs4, %temp;
}
	.loc 1 28 221
	st.global.v4.u16 	[%rd6], {%rs1, %rs1, %rs1, %rs4};

BB0_4:
	.loc 1 28 2
	ret;
}


