//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Effects/Sharpen.cu", 1399785316, 2597
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref inSrcTexture;
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry SharpenKernel(
	.param .u64 SharpenKernel_param_0,
	.param .u64 SharpenKernel_param_1,
	.param .u32 SharpenKernel_param_2,
	.param .u32 SharpenKernel_param_3,
	.param .u32 SharpenKernel_param_4,
	.param .u32 SharpenKernel_param_5,
	.param .f32 SharpenKernel_param_6,
	.param .f32 SharpenKernel_param_7
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<59>;
	.reg .s64 	%rd<17>;


	ld.param.u64 	%rd2, [SharpenKernel_param_1];
	ld.param.u32 	%r4, [SharpenKernel_param_2];
	ld.param.u32 	%r5, [SharpenKernel_param_3];
	ld.param.u32 	%r6, [SharpenKernel_param_4];
	ld.param.u32 	%r7, [SharpenKernel_param_5];
	ld.param.f32 	%f9, [SharpenKernel_param_6];
	ld.param.f32 	%f10, [SharpenKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 27 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	.loc 1 27 1
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 27 1
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 27 1
	cvt.rn.f32.s32	%f41, %r1;
	add.ftz.f32 	%f39, %f41, 0f3F000000;
	cvt.rn.f32.s32	%f42, %r2;
	add.ftz.f32 	%f16, %f42, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f11, %f12, %f13, %f14}, [inSrcTexture, {%f39, %f16}];
	// inline asm
	.loc 1 27 1
	add.ftz.f32 	%f21, %f41, 0fBF000000;
	add.ftz.f32 	%f34, %f42, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [inSrcTexture, {%f21, %f34}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [inSrcTexture, {%f39, %f34}];
	// inline asm
	.loc 1 27 1
	add.ftz.f32 	%f33, %f41, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [inSrcTexture, {%f33, %f34}];
	// inline asm
	.loc 1 27 1
	add.ftz.f32 	%f40, %f42, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f35, %f36, %f37, %f38}, [inSrcTexture, {%f39, %f40}];
	// inline asm
	.loc 1 27 1
	add.ftz.f32 	%f43, %f11, %f17;
	add.ftz.f32 	%f44, %f12, %f18;
	add.ftz.f32 	%f45, %f13, %f19;
	add.ftz.f32 	%f46, %f14, %f20;
	add.ftz.f32 	%f47, %f43, %f29;
	add.ftz.f32 	%f48, %f44, %f30;
	add.ftz.f32 	%f49, %f45, %f31;
	add.ftz.f32 	%f50, %f46, %f32;
	add.ftz.f32 	%f51, %f47, %f35;
	add.ftz.f32 	%f52, %f48, %f36;
	add.ftz.f32 	%f53, %f49, %f37;
	add.ftz.f32 	%f54, %f50, %f38;
	mul.ftz.f32 	%f55, %f51, %f10;
	mul.ftz.f32 	%f56, %f52, %f10;
	mul.ftz.f32 	%f57, %f53, %f10;
	mul.ftz.f32 	%f58, %f54, %f10;
	fma.rn.ftz.f32 	%f1, %f23, %f9, %f55;
	fma.rn.ftz.f32 	%f2, %f24, %f9, %f56;
	fma.rn.ftz.f32 	%f3, %f25, %f9, %f57;
	fma.rn.ftz.f32 	%f4, %f26, %f9, %f58;
	.loc 1 27 1
	mad.lo.s32 	%r3, %r2, %r4, %r1;
	.loc 1 27 1
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB0_3;

	mul.wide.s32 	%rd13, %r3, 16;
	add.s64 	%rd14, %rd1, %rd13;
	.loc 1 27 1
	st.global.v4.f32 	[%rd14], {%f1, %f2, %f3, %f4};
	bra.uni 	BB0_4;

BB0_3:
	mul.wide.s32 	%rd15, %r3, 8;
	add.s64 	%rd16, %rd1, %rd15;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f1;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f2;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs4, %temp;
}
	.loc 1 27 231
	st.global.v4.u16 	[%rd16], {%rs1, %rs2, %rs3, %rs4};

BB0_4:
	.loc 1 27 2
	ret;
}


