//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/SecondaryPass4.cu", 1399785249, 4299
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
.global .texref texture1_RECT;
// ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_SecondaryPass4(
	.param .u64 ShaderKernel_SecondaryPass4_param_0,
	.param .u32 ShaderKernel_SecondaryPass4_param_1,
	.param .u32 ShaderKernel_SecondaryPass4_param_2,
	.param .u32 ShaderKernel_SecondaryPass4_param_3,
	.param .u32 ShaderKernel_SecondaryPass4_param_4,
	.param .u64 ShaderKernel_SecondaryPass4_param_5,
	.param .u64 ShaderKernel_SecondaryPass4_param_6,
	.param .u64 ShaderKernel_SecondaryPass4_param_7
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<181>;
	.reg .s64 	%rd<34>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local[144];

	ld.param.u64 	%rd4, [ShaderKernel_SecondaryPass4_param_0];
	ld.param.u32 	%r4, [ShaderKernel_SecondaryPass4_param_1];
	ld.param.u32 	%r5, [ShaderKernel_SecondaryPass4_param_2];
	ld.param.u32 	%r6, [ShaderKernel_SecondaryPass4_param_3];
	ld.param.u32 	%r7, [ShaderKernel_SecondaryPass4_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_SecondaryPass4_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 36 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 36 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 36 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 36 1
	cvt.rn.f32.s32	%f11, %r2;
	add.ftz.f32 	%f1, %f11, 0f3F000000;
	cvt.rn.f32.s32	%f12, %r3;
	add.ftz.f32 	%f2, %f12, 0f3F000000;
	.loc 1 36 1
	setp.gt.u32	%p4, %r1, 8;
	@%p4 bra 	BB0_3;

	.loc 1 36 1
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd2, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f13, %f14, %f15, %f16};

BB0_3:
	.loc 1 36 1
	bar.sync 	0;
	.loc 1 36 111
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f73, %f1, 0f00000000;
	add.ftz.f32 	%f32, %f2, 0fBF800000;
	.loc 1 36 111
	// inline asm
	tex.2d.v4.f32.f32 {%f27, %f28, %f29, %f30}, [texture0_RECT, {%f73, %f32}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f38, %f2, 0fC0000000;
	.loc 1 36 111
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [texture0_RECT, {%f73, %f38}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f44, %f2, 0fC0400000;
	.loc 1 36 111
	// inline asm
	tex.2d.v4.f32.f32 {%f39, %f40, %f41, %f42}, [texture0_RECT, {%f73, %f44}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f50, %f2, 0fC0800000;
	.loc 1 36 119
	// inline asm
	tex.2d.v4.f32.f32 {%f45, %f46, %f47, %f48}, [texture0_RECT, {%f73, %f50}];
	// inline asm
	.loc 1 36 1
	ld.shared.v4.f32 	{%f81, %f82, %f83, %f84}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+32];
	.loc 1 36 1
	mul.ftz.f32 	%f86, %f30, %f81;
	mul.ftz.f32 	%f88, %f36, %f82;
	mul.ftz.f32 	%f90, %f42, %f83;
	mul.ftz.f32 	%f92, %f48, %f84;
	.loc 1 36 1
	add.ftz.f32 	%f56, %f2, 0f3F800000;
	mov.f32 	%f93, 0f3F800000;
	.loc 1 36 119
	// inline asm
	tex.2d.v4.f32.f32 {%f51, %f52, %f53, %f54}, [texture0_RECT, {%f73, %f56}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f62, %f2, 0f40000000;
	.loc 1 36 119
	// inline asm
	tex.2d.v4.f32.f32 {%f57, %f58, %f59, %f60}, [texture0_RECT, {%f73, %f62}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f68, %f2, 0f40400000;
	.loc 1 36 119
	// inline asm
	tex.2d.v4.f32.f32 {%f63, %f64, %f65, %f66}, [texture0_RECT, {%f73, %f68}];
	// inline asm
	.loc 1 36 1
	add.ftz.f32 	%f74, %f2, 0f40800000;
	.loc 1 36 119
	// inline asm
	tex.2d.v4.f32.f32 {%f69, %f70, %f71, %f72}, [texture0_RECT, {%f73, %f74}];
	// inline asm
	.loc 1 36 1
	fma.rn.ftz.f32 	%f94, %f54, %f81, %f86;
	fma.rn.ftz.f32 	%f95, %f60, %f82, %f88;
	fma.rn.ftz.f32 	%f96, %f66, %f83, %f90;
	fma.rn.ftz.f32 	%f97, %f72, %f84, %f92;
	.loc 1 36 1
	add.ftz.f32 	%f98, %f94, %f95;
	add.ftz.f32 	%f99, %f98, %f96;
	add.ftz.f32 	%f100, %f99, %f97;
	add.ftz.f32 	%f101, %f100, %f24;
	ld.shared.f32 	%f102, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+60];
	mul.ftz.f32 	%f103, %f101, %f102;
	.loc 1 36 119
	// inline asm
	tex.2d.v4.f32.f32 {%f75, %f76, %f77, %f78}, [texture1_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 36 1
	ld.shared.v4.f32 	{%f104, %f105, %f106, %f107}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+96];
	.loc 1 36 1
	mul.ftz.f32 	%f109, %f22, %f105;
	fma.rn.ftz.f32 	%f111, %f23, %f104, %f109;
	fma.rn.ftz.f32 	%f113, %f21, %f106, %f111;
	.loc 1 36 1
	sub.ftz.f32 	%f114, %f23, %f113;
	sub.ftz.f32 	%f115, %f22, %f113;
	sub.ftz.f32 	%f116, %f21, %f113;
	.loc 1 36 1
	ld.shared.v4.f32 	{%f117, %f118, %f119, %f120}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+112];
	.loc 1 36 1
	fma.rn.ftz.f32 	%f122, %f114, %f117, %f113;
	fma.rn.ftz.f32 	%f124, %f115, %f118, %f113;
	fma.rn.ftz.f32 	%f126, %f116, %f119, %f113;
	.loc 1 36 1
	ld.shared.v4.f32 	{%f127, %f128, %f129, %f130}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local];
	ld.shared.v4.f32 	{%f132, %f133, %f134, %f135}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+16];
	.loc 1 36 1
	fma.rn.ftz.f32 	%f137, %f122, %f132, %f127;
	fma.rn.ftz.f32 	%f140, %f124, %f133, %f128;
	fma.rn.ftz.f32 	%f143, %f126, %f134, %f129;
	.loc 1 36 1
	mul.ftz.f32 	%f144, %f140, %f105;
	fma.rn.ftz.f32 	%f145, %f137, %f104, %f144;
	fma.rn.ftz.f32 	%f146, %f143, %f106, %f145;
	.loc 1 36 1
	sub.ftz.f32 	%f147, %f137, %f146;
	sub.ftz.f32 	%f148, %f140, %f146;
	sub.ftz.f32 	%f149, %f143, %f146;
	.loc 1 36 1
	ld.shared.v4.f32 	{%f150, %f151, %f152, %f153}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+128];
	.loc 1 36 1
	fma.rn.ftz.f32 	%f155, %f147, %f150, %f146;
	fma.rn.ftz.f32 	%f157, %f148, %f151, %f146;
	fma.rn.ftz.f32 	%f159, %f149, %f152, %f146;
	.loc 1 36 1
	ld.shared.v4.f32 	{%f160, %f161, %f162, %f163}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+80];
	ld.shared.v4.f32 	{%f165, %f166, %f167, %f168}, [ShaderKernel_SecondaryPass4$__cuda_local_var_170274_639_non_const_p_local+64];
	.loc 1 36 1
	fma.rn.ftz.f32 	%f170, %f23, %f165, %f160;
	fma.rn.ftz.f32 	%f173, %f22, %f166, %f161;
	fma.rn.ftz.f32 	%f176, %f21, %f167, %f162;
	.loc 1 36 1
	sub.ftz.f32 	%f177, %f93, %f103;
	mul.ftz.f32 	%f178, %f177, %f170;
	fma.rn.ftz.f32 	%f3, %f103, %f155, %f178;
	mul.ftz.f32 	%f179, %f177, %f173;
	fma.rn.ftz.f32 	%f4, %f103, %f157, %f179;
	mul.ftz.f32 	%f180, %f177, %f176;
	fma.rn.ftz.f32 	%f5, %f103, %f159, %f180;
	.loc 1 36 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 36 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 36 1
	setp.eq.s32	%p5, %r5, 0;
	@%p5 bra 	BB0_5;

	.loc 1 36 1
	shl.b64 	%rd30, %rd3, 4;
	add.s64 	%rd31, %rd1, %rd30;
	st.global.v4.f32 	[%rd31], {%f5, %f4, %f3, %f78};
	bra.uni 	BB0_6;

BB0_5:
	.loc 1 36 1
	shl.b64 	%rd32, %rd3, 3;
	add.s64 	%rd33, %rd1, %rd32;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f78;
	mov.b16 	%rs4, %temp;
}
	.loc 1 36 241
	st.global.v4.u16 	[%rd33], {%rs1, %rs2, %rs3, %rs4};

BB0_6:
	.loc 1 36 2
	ret;
}


