//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Filters/Source/RemoveFlickerSource.cu", 1399785316, 2336
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref inSrcTexture;
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry RemoveFlickerKernel(
	.param .u64 RemoveFlickerKernel_param_0,
	.param .u64 RemoveFlickerKernel_param_1,
	.param .u32 RemoveFlickerKernel_param_2,
	.param .u32 RemoveFlickerKernel_param_3,
	.param .u32 RemoveFlickerKernel_param_4,
	.param .u32 RemoveFlickerKernel_param_5
)
{
	.reg .pred 	%p<8>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<15>;
	.reg .f32 	%f<58>;
	.reg .s64 	%rd<12>;


	ld.param.u64 	%rd2, [RemoveFlickerKernel_param_1];
	ld.param.u32 	%r4, [RemoveFlickerKernel_param_2];
	ld.param.u32 	%r5, [RemoveFlickerKernel_param_3];
	ld.param.u32 	%r7, [RemoveFlickerKernel_param_4];
	ld.param.u32 	%r6, [RemoveFlickerKernel_param_5];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 28 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	.loc 1 28 1
	setp.lt.s32	%p1, %r1, %r7;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	.loc 1 28 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 28 1
	cvt.rn.f32.s32	%f33, %r1;
	add.ftz.f32 	%f31, %f33, 0f3F000000;
	cvt.rn.f32.s32	%f2, %r2;
	add.ftz.f32 	%f32, %f2, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f27, %f28, %f29, %f30}, [inSrcTexture, {%f31, %f32}];
	// inline asm
	.loc 1 28 1
	add.s32 	%r14, %r6, -1;
	setp.ne.s32	%p4, %r2, %r14;
	setp.ne.s32	%p5, %r2, 0;
	and.pred  	%p6, %p4, %p5;
	mov.f32 	%f57, %f30;
	mov.f32 	%f56, %f29;
	mov.f32 	%f55, %f28;
	mov.f32 	%f54, %f27;
	.loc 1 28 1
	@!%p6 bra 	BB0_3;
	bra.uni 	BB0_2;

BB0_2:
	.loc 1 28 1
	add.ftz.f32 	%f39, %f2, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f34, %f35, %f36, %f37}, [inSrcTexture, {%f31, %f39}];
	// inline asm
	.loc 1 28 1
	add.ftz.f32 	%f45, %f2, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f40, %f41, %f42, %f43}, [inSrcTexture, {%f31, %f45}];
	// inline asm
	.loc 1 28 1
	add.ftz.f32 	%f46, %f34, %f40;
	add.ftz.f32 	%f47, %f35, %f41;
	add.ftz.f32 	%f48, %f36, %f42;
	add.ftz.f32 	%f49, %f37, %f43;
	mul.ftz.f32 	%f50, %f46, 0f3E800000;
	mul.ftz.f32 	%f51, %f47, 0f3E800000;
	mul.ftz.f32 	%f52, %f48, 0f3E800000;
	mul.ftz.f32 	%f53, %f49, 0f3E800000;
	fma.rn.ftz.f32 	%f54, %f27, 0f3F000000, %f50;
	fma.rn.ftz.f32 	%f55, %f28, 0f3F000000, %f51;
	fma.rn.ftz.f32 	%f56, %f29, 0f3F000000, %f52;
	fma.rn.ftz.f32 	%f57, %f30, 0f3F000000, %f53;

BB0_3:
	.loc 1 28 1
	mad.lo.s32 	%r3, %r2, %r4, %r1;
	.loc 1 28 1
	setp.eq.s32	%p7, %r5, 0;
	@%p7 bra 	BB0_5;

	mul.wide.s32 	%rd8, %r3, 16;
	add.s64 	%rd9, %rd1, %rd8;
	.loc 1 28 1
	st.global.v4.f32 	[%rd9], {%f54, %f55, %f56, %f57};
	bra.uni 	BB0_6;

BB0_5:
	mul.wide.s32 	%rd10, %r3, 8;
	add.s64 	%rd11, %rd1, %rd10;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f54;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f55;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f56;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f57;
	mov.b16 	%rs4, %temp;
}
	.loc 1 28 231
	st.global.v4.u16 	[%rd11], {%rs1, %rs2, %rs3, %rs4};

BB0_6:
	.loc 1 28 2
	ret;
}


