//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Filters/Source/InvertAlphaSource.cu", 1399785316, 1927
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry InvertAlphaKernel(
	.param .u64 InvertAlphaKernel_param_0,
	.param .u32 InvertAlphaKernel_param_1,
	.param .u32 InvertAlphaKernel_param_2,
	.param .u32 InvertAlphaKernel_param_3,
	.param .u32 InvertAlphaKernel_param_4
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<31>;
	.reg .s64 	%rd<7>;


	ld.param.u64 	%rd4, [InvertAlphaKernel_param_0];
	ld.param.u32 	%r3, [InvertAlphaKernel_param_1];
	ld.param.u32 	%r4, [InvertAlphaKernel_param_2];
	ld.param.u32 	%r5, [InvertAlphaKernel_param_3];
	ld.param.u32 	%r6, [InvertAlphaKernel_param_4];
	cvta.to.global.u64 	%rd1, %rd4;
	.loc 1 27 1
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	.loc 1 27 1
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	.loc 1 27 1
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 27 1
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	mul.wide.s32 	%rd5, %r13, 16;
	add.s64 	%rd2, %rd1, %rd5;
	mul.wide.s32 	%rd6, %r13, 8;
	add.s64 	%rd3, %rd1, %rd6;
	.loc 1 27 1
	setp.eq.s32	%p4, %r4, 0;
	@%p4 bra 	BB0_3;

	ld.global.v4.f32 	{%f21, %f22, %f23, %f24}, [%rd2];
	mov.f32 	%f30, %f24;
	mov.f32 	%f29, %f23;
	mov.f32 	%f28, %f22;
	mov.f32 	%f27, %f21;
	bra.uni 	BB0_4;

BB0_3:
	.loc 1 27 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd3];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f27, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f28, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f29, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f30, %temp;
	}

BB0_4:
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f25, %f30;
	mov.f32 	%f26, 0f3F800000;
	.loc 1 27 124
	sub.ftz.f32 	%f20, %f26, %f25;
	.loc 1 27 1
	@%p4 bra 	BB0_6;

	.loc 1 27 1
	st.global.v4.f32 	[%rd2], {%f27, %f28, %f29, %f20};
	bra.uni 	BB0_7;

BB0_6:
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f27;
	mov.b16 	%rs9, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f28;
	mov.b16 	%rs10, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f29;
	mov.b16 	%rs11, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs12, %temp;
}
	.loc 1 27 231
	st.global.v4.u16 	[%rd3], {%rs9, %rs10, %rs11, %rs12};

BB0_7:
	.loc 1 27 2
	ret;
}


