//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxTinting.cu", 1399785249, 3015
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxTinting(
	.param .u64 ShaderKernel_fxTinting_param_0,
	.param .u32 ShaderKernel_fxTinting_param_1,
	.param .u32 ShaderKernel_fxTinting_param_2,
	.param .u32 ShaderKernel_fxTinting_param_3,
	.param .u32 ShaderKernel_fxTinting_param_4,
	.param .u64 ShaderKernel_fxTinting_param_5,
	.param .u64 ShaderKernel_fxTinting_param_6
)
{
	.reg .pred 	%p<30>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<128>;
	.reg .s64 	%rd<15>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local[112];

	ld.param.u64 	%rd4, [ShaderKernel_fxTinting_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxTinting_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxTinting_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxTinting_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxTinting_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxTinting_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 34 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 34 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 34 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 34 1
	cvt.rn.f32.s32	%f11, %r2;
	add.ftz.f32 	%f1, %f11, 0f3F000000;
	cvt.rn.f32.s32	%f12, %r3;
	add.ftz.f32 	%f2, %f12, 0f3F000000;
	.loc 1 34 1
	setp.gt.u32	%p4, %r1, 6;
	@%p4 bra 	BB0_3;

	.loc 1 34 1
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd2, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f13, %f14, %f15, %f16};

BB0_3:
	.loc 1 34 1
	bar.sync 	0;
	.loc 1 34 105
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	mov.f32 	%f27, 0f3F800000;
	.loc 1 34 1
	sub.ftz.f32 	%f28, %f27, %f23;
	sub.ftz.f32 	%f29, %f27, %f22;
	sub.ftz.f32 	%f30, %f27, %f21;
	sub.ftz.f32 	%f31, %f27, %f24;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f32, %f33, %f34, %f35}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local+16];
	.loc 1 34 1
	mul.ftz.f32 	%f37, %f28, %f32;
	mul.ftz.f32 	%f39, %f29, %f33;
	mul.ftz.f32 	%f41, %f30, %f34;
	mul.ftz.f32 	%f43, %f31, %f35;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f44, %f45, %f46, %f47}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local];
	.loc 1 34 1
	mul.ftz.f32 	%f49, %f23, %f44;
	mul.ftz.f32 	%f51, %f22, %f45;
	mul.ftz.f32 	%f53, %f21, %f46;
	mul.ftz.f32 	%f55, %f24, %f47;
	.loc 1 34 1
	add.ftz.f32 	%f56, %f23, %f44;
	add.ftz.f32 	%f57, %f22, %f45;
	add.ftz.f32 	%f58, %f21, %f46;
	add.ftz.f32 	%f59, %f24, %f47;
	.loc 1 34 1
	sub.ftz.f32 	%f60, %f27, %f37;
	sub.ftz.f32 	%f61, %f27, %f39;
	sub.ftz.f32 	%f62, %f27, %f41;
	sub.ftz.f32 	%f63, %f27, %f43;
	.loc 1 34 1
	setp.gt.ftz.f32	%p5, %f23, %f44;
	selp.f32	%f64, %f23, %f44, %p5;
	setp.gt.ftz.f32	%p6, %f22, %f45;
	selp.f32	%f65, %f22, %f45, %p6;
	setp.gt.ftz.f32	%p7, %f21, %f46;
	selp.f32	%f66, %f21, %f46, %p7;
	setp.gt.ftz.f32	%p8, %f24, %f47;
	selp.f32	%f67, %f24, %f47, %p8;
	.loc 1 34 1
	selp.f32	%f68, %f44, %f23, %p5;
	selp.f32	%f69, %f45, %f22, %p6;
	selp.f32	%f70, %f46, %f21, %p7;
	selp.f32	%f71, %f47, %f24, %p8;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f72, %f73, %f74, %f75}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local+32];
	.loc 1 34 1
	setp.lt.ftz.f32	%p9, %f72, 0f00000000;
	selp.f32	%f77, %f44, %f49, %p9;
	setp.lt.ftz.f32	%p10, %f73, 0f00000000;
	selp.f32	%f79, %f45, %f51, %p10;
	setp.lt.ftz.f32	%p11, %f74, 0f00000000;
	selp.f32	%f81, %f46, %f53, %p11;
	setp.lt.ftz.f32	%p12, %f75, 0f00000000;
	selp.f32	%f83, %f47, %f55, %p12;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f84, %f85, %f86, %f87}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local+48];
	.loc 1 34 1
	setp.lt.ftz.f32	%p13, %f84, 0f00000000;
	selp.f32	%f89, %f77, %f56, %p13;
	setp.lt.ftz.f32	%p14, %f85, 0f00000000;
	selp.f32	%f91, %f79, %f57, %p14;
	setp.lt.ftz.f32	%p15, %f86, 0f00000000;
	selp.f32	%f93, %f81, %f58, %p15;
	setp.lt.ftz.f32	%p16, %f87, 0f00000000;
	selp.f32	%f95, %f83, %f59, %p16;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f96, %f97, %f98, %f99}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local+64];
	.loc 1 34 1
	setp.lt.ftz.f32	%p17, %f96, 0f00000000;
	selp.f32	%f101, %f89, %f60, %p17;
	setp.lt.ftz.f32	%p18, %f97, 0f00000000;
	selp.f32	%f103, %f91, %f61, %p18;
	setp.lt.ftz.f32	%p19, %f98, 0f00000000;
	selp.f32	%f105, %f93, %f62, %p19;
	setp.lt.ftz.f32	%p20, %f99, 0f00000000;
	selp.f32	%f107, %f95, %f63, %p20;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f108, %f109, %f110, %f111}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local+80];
	.loc 1 34 1
	setp.lt.ftz.f32	%p21, %f108, 0f00000000;
	selp.f32	%f113, %f101, %f64, %p21;
	setp.lt.ftz.f32	%p22, %f109, 0f00000000;
	selp.f32	%f115, %f103, %f65, %p22;
	setp.lt.ftz.f32	%p23, %f110, 0f00000000;
	selp.f32	%f117, %f105, %f66, %p23;
	setp.lt.ftz.f32	%p24, %f111, 0f00000000;
	selp.f32	%f119, %f107, %f67, %p24;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f120, %f121, %f122, %f123}, [ShaderKernel_fxTinting$__cuda_local_var_170272_469_non_const_p_local+96];
	.loc 1 34 1
	setp.lt.ftz.f32	%p25, %f120, 0f00000000;
	selp.f32	%f9, %f113, %f68, %p25;
	setp.lt.ftz.f32	%p26, %f121, 0f00000000;
	selp.f32	%f8, %f115, %f69, %p26;
	setp.lt.ftz.f32	%p27, %f122, 0f00000000;
	selp.f32	%f7, %f117, %f70, %p27;
	setp.lt.ftz.f32	%p28, %f123, 0f00000000;
	selp.f32	%f10, %f119, %f71, %p28;
	.loc 1 34 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 34 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 34 1
	setp.eq.s32	%p29, %r5, 0;
	@%p29 bra 	BB0_5;

	.loc 1 34 1
	shl.b64 	%rd11, %rd3, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f7, %f8, %f9, %f10};
	bra.uni 	BB0_6;

BB0_5:
	.loc 1 34 1
	shl.b64 	%rd13, %rd3, 3;
	add.s64 	%rd14, %rd1, %rd13;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f7;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f8;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f9;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f10;
	mov.b16 	%rs4, %temp;
}
	.loc 1 34 231
	st.global.v4.u16 	[%rd14], {%rs1, %rs2, %rs3, %rs4};

BB0_6:
	.loc 1 34 2
	ret;
}


