//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxTechnicolor2strip.cu", 1399785249, 2097
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxTechnicolor2strip(
	.param .u64 ShaderKernel_fxTechnicolor2strip_param_0,
	.param .u32 ShaderKernel_fxTechnicolor2strip_param_1,
	.param .u32 ShaderKernel_fxTechnicolor2strip_param_2,
	.param .u32 ShaderKernel_fxTechnicolor2strip_param_3,
	.param .u32 ShaderKernel_fxTechnicolor2strip_param_4,
	.param .u64 ShaderKernel_fxTechnicolor2strip_param_5,
	.param .u64 ShaderKernel_fxTechnicolor2strip_param_6
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<4>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<18>;
	.reg .s64 	%rd<8>;


	ld.param.u64 	%rd2, [ShaderKernel_fxTechnicolor2strip_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxTechnicolor2strip_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxTechnicolor2strip_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxTechnicolor2strip_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxTechnicolor2strip_param_4];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 24 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	.loc 1 24 1
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 24 1
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 24 1
	cvt.rn.f32.s32	%f14, %r1;
	add.ftz.f32 	%f12, %f14, 0f3F000000;
	cvt.rn.f32.s32	%f15, %r2;
	add.ftz.f32 	%f13, %f15, 0f3F000000;
	.loc 1 24 105
	// inline asm
	tex.2d.v4.f32.f32 {%f8, %f9, %f10, %f11}, [texture0_RECT, {%f12, %f13}];
	// inline asm
	.loc 1 24 1
	mul.ftz.f32 	%f16, %f9, 0f3F4CCCCD;
	fma.rn.ftz.f32 	%f17, %f10, 0f00000000, %f16;
	fma.rn.ftz.f32 	%f2, %f8, 0f3E4CCCCD, %f17;
	.loc 1 24 1
	mad.lo.s32 	%r3, %r2, %r4, %r1;
	.loc 1 24 1
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB0_3;

	mul.wide.s32 	%rd4, %r3, 16;
	add.s64 	%rd5, %rd1, %rd4;
	.loc 1 24 1
	st.global.v4.f32 	[%rd5], {%f2, %f2, %f10, %f11};
	bra.uni 	BB0_4;

BB0_3:
	mul.wide.s32 	%rd6, %r3, 8;
	add.s64 	%rd7, %rd1, %rd6;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f2;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f10;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f11;
	mov.b16 	%rs3, %temp;
}
	.loc 1 24 231
	st.global.v4.u16 	[%rd7], {%rs1, %rs1, %rs2, %rs3};

BB0_4:
	.loc 1 24 2
	ret;
}


