//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxPaletteCut.cu", 1399785249, 2495
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_fxPaletteCut$__cuda_local_var_170267_472_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxPaletteCut(
	.param .u64 ShaderKernel_fxPaletteCut_param_0,
	.param .u32 ShaderKernel_fxPaletteCut_param_1,
	.param .u32 ShaderKernel_fxPaletteCut_param_2,
	.param .u32 ShaderKernel_fxPaletteCut_param_3,
	.param .u32 ShaderKernel_fxPaletteCut_param_4,
	.param .u64 ShaderKernel_fxPaletteCut_param_5,
	.param .u64 ShaderKernel_fxPaletteCut_param_6
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<50>;
	.reg .s64 	%rd<15>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxPaletteCut$__cuda_local_var_170267_472_non_const_p_local[32];

	ld.param.u64 	%rd4, [ShaderKernel_fxPaletteCut_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxPaletteCut_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxPaletteCut_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxPaletteCut_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxPaletteCut_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxPaletteCut_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 29 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 29 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 29 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 29 1
	cvt.rn.f32.s32	%f11, %r2;
	add.ftz.f32 	%f1, %f11, 0f3F000000;
	cvt.rn.f32.s32	%f12, %r3;
	add.ftz.f32 	%f2, %f12, 0f3F000000;
	.loc 1 29 1
	setp.gt.u32	%p4, %r1, 1;
	@%p4 bra 	BB0_3;

	.loc 1 29 1
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxPaletteCut$__cuda_local_var_170267_472_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd2, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f13, %f14, %f15, %f16};

BB0_3:
	.loc 1 29 1
	bar.sync 	0;
	.loc 1 29 105
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f27, %f23;
	cvt.ftz.sat.f32.f32	%f28, %f22;
	cvt.ftz.sat.f32.f32	%f29, %f21;
	.loc 1 29 1
	ld.shared.v4.f32 	{%f30, %f31, %f32, %f33}, [ShaderKernel_fxPaletteCut$__cuda_local_var_170267_472_non_const_p_local];
	.loc 1 29 1
	fma.rn.ftz.f32 	%f35, %f27, %f30, 0f3F000000;
	fma.rn.ftz.f32 	%f37, %f28, %f31, 0f3F000000;
	fma.rn.ftz.f32 	%f39, %f29, %f32, 0f3F000000;
	.loc 2 2740 10
	cvt.rmi.ftz.f32.f32	%f40, %f35;
	cvt.rmi.ftz.f32.f32	%f41, %f37;
	cvt.rmi.ftz.f32.f32	%f42, %f39;
	.loc 1 29 1
	ld.shared.v4.f32 	{%f43, %f44, %f45, %f46}, [ShaderKernel_fxPaletteCut$__cuda_local_var_170267_472_non_const_p_local+16];
	.loc 1 29 1
	mul.ftz.f32 	%f9, %f40, %f43;
	mul.ftz.f32 	%f8, %f41, %f44;
	mul.ftz.f32 	%f7, %f42, %f45;
	.loc 1 29 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 29 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 29 1
	setp.eq.s32	%p5, %r5, 0;
	@%p5 bra 	BB0_5;

	.loc 1 29 1
	shl.b64 	%rd11, %rd3, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f7, %f8, %f9, %f24};
	bra.uni 	BB0_6;

BB0_5:
	.loc 1 29 1
	shl.b64 	%rd13, %rd3, 3;
	add.s64 	%rd14, %rd1, %rd13;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f7;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f8;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f9;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f24;
	mov.b16 	%rs4, %temp;
}
	.loc 1 29 231
	st.global.v4.u16 	[%rd14], {%rs1, %rs2, %rs3, %rs4};

BB0_6:
	.loc 1 29 2
	ret;
}


