//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxOutline.cu", 1399785249, 3411
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_fxOutline$__cuda_local_var_170266_469_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxOutline(
	.param .u64 ShaderKernel_fxOutline_param_0,
	.param .u32 ShaderKernel_fxOutline_param_1,
	.param .u32 ShaderKernel_fxOutline_param_2,
	.param .u32 ShaderKernel_fxOutline_param_3,
	.param .u32 ShaderKernel_fxOutline_param_4,
	.param .u64 ShaderKernel_fxOutline_param_5,
	.param .u64 ShaderKernel_fxOutline_param_6
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<120>;
	.reg .s64 	%rd<28>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxOutline$__cuda_local_var_170266_469_non_const_p_local[16];

	ld.param.u64 	%rd4, [ShaderKernel_fxOutline_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxOutline_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxOutline_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxOutline_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxOutline_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxOutline_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 28 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 28 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 28 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 28 1
	cvt.rn.f32.s32	%f11, %r2;
	add.ftz.f32 	%f1, %f11, 0f3F000000;
	cvt.rn.f32.s32	%f12, %r3;
	add.ftz.f32 	%f2, %f12, 0f3F000000;
	.loc 1 28 1
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	.loc 1 28 1
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd2];
	st.shared.v4.f32 	[ShaderKernel_fxOutline$__cuda_local_var_170266_469_non_const_p_local], {%f13, %f14, %f15, %f16};

BB0_3:
	.loc 1 28 1
	bar.sync 	0;
	.loc 1 28 1
	add.ftz.f32 	%f67, %f1, 0f3F800000;
	mov.f32 	%f75, 0f3F800000;
	.loc 1 28 1
	add.ftz.f32 	%f44, %f2, 0fBF800000;
	.loc 1 28 111
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f67, %f44}];
	// inline asm
	.loc 1 28 1
	add.ftz.f32 	%f62, %f2, 0f3F800000;
	add.ftz.f32 	%f49, %f1, 0fBF800000;
	.loc 1 28 111
	// inline asm
	tex.2d.v4.f32.f32 {%f27, %f28, %f29, %f30}, [texture0_RECT, {%f49, %f62}];
	// inline asm
	.loc 1 28 1
	sub.ftz.f32 	%f76, %f23, %f29;
	sub.ftz.f32 	%f77, %f22, %f28;
	sub.ftz.f32 	%f78, %f21, %f27;
	.loc 1 28 111
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [texture0_RECT, {%f49, %f44}];
	// inline asm
	.loc 1 28 1
	sub.ftz.f32 	%f79, %f76, %f35;
	sub.ftz.f32 	%f80, %f77, %f34;
	sub.ftz.f32 	%f81, %f78, %f33;
	.loc 1 28 1
	add.ftz.f32 	%f82, %f35, %f76;
	add.ftz.f32 	%f83, %f34, %f77;
	add.ftz.f32 	%f84, %f33, %f78;
	.loc 1 28 1
	add.ftz.f32 	%f55, %f1, 0f00000000;
	.loc 1 28 113
	// inline asm
	tex.2d.v4.f32.f32 {%f39, %f40, %f41, %f42}, [texture0_RECT, {%f55, %f44}];
	// inline asm
	.loc 1 28 1
	fma.rn.ftz.f32 	%f85, %f41, 0f40000000, %f82;
	fma.rn.ftz.f32 	%f86, %f40, 0f40000000, %f83;
	fma.rn.ftz.f32 	%f87, %f39, 0f40000000, %f84;
	.loc 1 28 1
	add.ftz.f32 	%f68, %f2, 0f00000000;
	.loc 1 28 119
	// inline asm
	tex.2d.v4.f32.f32 {%f45, %f46, %f47, %f48}, [texture0_RECT, {%f49, %f68}];
	// inline asm
	.loc 1 28 1
	fma.rn.ftz.f32 	%f88, %f47, 0fC0000000, %f79;
	fma.rn.ftz.f32 	%f89, %f46, 0fC0000000, %f80;
	fma.rn.ftz.f32 	%f90, %f45, 0fC0000000, %f81;
	.loc 1 28 119
	// inline asm
	tex.2d.v4.f32.f32 {%f51, %f52, %f53, %f54}, [texture0_RECT, {%f55, %f62}];
	// inline asm
	.loc 1 28 1
	fma.rn.ftz.f32 	%f91, %f53, 0fC0000000, %f85;
	fma.rn.ftz.f32 	%f92, %f52, 0fC0000000, %f86;
	fma.rn.ftz.f32 	%f93, %f51, 0fC0000000, %f87;
	.loc 1 28 119
	// inline asm
	tex.2d.v4.f32.f32 {%f57, %f58, %f59, %f60}, [texture0_RECT, {%f67, %f62}];
	// inline asm
	.loc 1 28 1
	sub.ftz.f32 	%f94, %f91, %f59;
	sub.ftz.f32 	%f95, %f92, %f58;
	sub.ftz.f32 	%f96, %f93, %f57;
	.loc 1 28 1
	add.ftz.f32 	%f97, %f59, %f88;
	add.ftz.f32 	%f98, %f58, %f89;
	add.ftz.f32 	%f99, %f57, %f90;
	.loc 1 28 119
	// inline asm
	tex.2d.v4.f32.f32 {%f63, %f64, %f65, %f66}, [texture0_RECT, {%f67, %f68}];
	// inline asm
	.loc 1 28 1
	fma.rn.ftz.f32 	%f100, %f65, 0f40000000, %f97;
	fma.rn.ftz.f32 	%f101, %f64, 0f40000000, %f98;
	fma.rn.ftz.f32 	%f102, %f63, 0f40000000, %f99;
	.loc 1 28 1
	mul.ftz.f32 	%f103, %f100, %f100;
	mul.ftz.f32 	%f104, %f101, %f101;
	mul.ftz.f32 	%f105, %f102, %f102;
	.loc 1 28 1
	fma.rn.ftz.f32 	%f106, %f94, %f94, %f103;
	fma.rn.ftz.f32 	%f107, %f95, %f95, %f104;
	fma.rn.ftz.f32 	%f108, %f96, %f96, %f105;
	.loc 1 28 1
	add.ftz.f32 	%f109, %f106, %f107;
	add.ftz.f32 	%f110, %f109, %f108;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f111, %f110;
	.loc 1 28 1
	setp.gt.ftz.f32	%p5, %f111, 0f322BCC77;
	selp.f32	%f112, %f111, 0f322BCC77, %p5;
	.loc 2 2775 10
	rsqrt.approx.ftz.f32 	%f113, %f112;
	.loc 1 28 1
	mul.ftz.f32 	%f114, %f113, %f112;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f115, %f114;
	.loc 1 28 1
	ld.shared.f32 	%f116, [ShaderKernel_fxOutline$__cuda_local_var_170266_469_non_const_p_local];
	mul.ftz.f32 	%f117, %f115, %f116;
	.loc 2 2740 10
	cvt.rmi.ftz.f32.f32	%f118, %f117;
	.loc 1 28 1
	sub.ftz.f32 	%f119, %f75, %f118;
	.loc 1 28 119
	// inline asm
	tex.2d.v4.f32.f32 {%f69, %f70, %f71, %f72}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 28 1
	mul.ftz.f32 	%f9, %f119, %f71;
	mul.ftz.f32 	%f8, %f119, %f70;
	mul.ftz.f32 	%f7, %f119, %f69;
	.loc 1 28 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 28 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 28 1
	setp.eq.s32	%p6, %r5, 0;
	@%p6 bra 	BB0_5;

	.loc 1 28 1
	shl.b64 	%rd24, %rd3, 4;
	add.s64 	%rd25, %rd1, %rd24;
	st.global.v4.f32 	[%rd25], {%f7, %f8, %f9, %f72};
	bra.uni 	BB0_6;

BB0_5:
	.loc 1 28 1
	shl.b64 	%rd26, %rd3, 3;
	add.s64 	%rd27, %rd1, %rd26;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f7;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f8;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f9;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f72;
	mov.b16 	%rs4, %temp;
}
	.loc 1 28 241
	st.global.v4.u16 	[%rd27], {%rs1, %rs2, %rs3, %rs4};

BB0_6:
	.loc 1 28 2
	ret;
}


