//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxMedianFilter3x3V.cu", 1399785249, 2344
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxMedianFilter3x3V(
	.param .u64 ShaderKernel_fxMedianFilter3x3V_param_0,
	.param .u32 ShaderKernel_fxMedianFilter3x3V_param_1,
	.param .u32 ShaderKernel_fxMedianFilter3x3V_param_2,
	.param .u32 ShaderKernel_fxMedianFilter3x3V_param_3,
	.param .u32 ShaderKernel_fxMedianFilter3x3V_param_4,
	.param .u64 ShaderKernel_fxMedianFilter3x3V_param_5,
	.param .u64 ShaderKernel_fxMedianFilter3x3V_param_6
)
{
	.reg .pred 	%p<17>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<41>;
	.reg .s64 	%rd<13>;


	ld.param.u64 	%rd2, [ShaderKernel_fxMedianFilter3x3V_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxMedianFilter3x3V_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxMedianFilter3x3V_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxMedianFilter3x3V_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxMedianFilter3x3V_param_4];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 24 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	.loc 1 24 1
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 24 1
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 24 1
	cvt.rn.f32.s32	%f27, %r1;
	add.ftz.f32 	%f19, %f27, 0f3F000000;
	cvt.rn.f32.s32	%f28, %r2;
	add.ftz.f32 	%f20, %f28, 0f3F000000;
	.loc 1 24 1
	add.ftz.f32 	%f25, %f19, 0f00000000;
	add.ftz.f32 	%f14, %f20, 0f3F800000;
	add.ftz.f32 	%f26, %f20, 0fBF800000;
	.loc 1 24 111
	// inline asm
	tex.2d.v4.f32.f32 {%f9, %f10, %f11, %f12}, [texture0_RECT, {%f25, %f14}];
	// inline asm
	.loc 1 24 111
	// inline asm
	tex.2d.v4.f32.f32 {%f15, %f16, %f17, %f18}, [texture0_RECT, {%f19, %f20}];
	// inline asm
	.loc 1 24 111
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f25, %f26}];
	// inline asm
	.loc 1 24 1
	setp.gt.ftz.f32	%p4, %f11, %f17;
	selp.f32	%f29, %f17, %f11, %p4;
	setp.gt.ftz.f32	%p5, %f10, %f16;
	selp.f32	%f30, %f16, %f10, %p5;
	setp.gt.ftz.f32	%p6, %f9, %f15;
	selp.f32	%f31, %f15, %f9, %p6;
	setp.gt.ftz.f32	%p7, %f12, %f18;
	selp.f32	%f32, %f18, %f12, %p7;
	.loc 1 24 1
	selp.f32	%f33, %f11, %f17, %p4;
	selp.f32	%f34, %f10, %f16, %p5;
	selp.f32	%f35, %f9, %f15, %p6;
	selp.f32	%f36, %f12, %f18, %p7;
	.loc 1 24 1
	setp.gt.ftz.f32	%p8, %f33, %f23;
	selp.f32	%f37, %f23, %f33, %p8;
	setp.gt.ftz.f32	%p9, %f34, %f22;
	selp.f32	%f38, %f22, %f34, %p9;
	setp.gt.ftz.f32	%p10, %f35, %f21;
	selp.f32	%f39, %f21, %f35, %p10;
	setp.gt.ftz.f32	%p11, %f36, %f24;
	selp.f32	%f40, %f24, %f36, %p11;
	.loc 1 24 1
	setp.gt.ftz.f32	%p12, %f29, %f37;
	selp.f32	%f7, %f29, %f37, %p12;
	setp.gt.ftz.f32	%p13, %f30, %f38;
	selp.f32	%f6, %f30, %f38, %p13;
	setp.gt.ftz.f32	%p14, %f31, %f39;
	selp.f32	%f5, %f31, %f39, %p14;
	setp.gt.ftz.f32	%p15, %f32, %f40;
	selp.f32	%f8, %f32, %f40, %p15;
	.loc 1 24 1
	mad.lo.s32 	%r3, %r2, %r4, %r1;
	.loc 1 24 1
	setp.eq.s32	%p16, %r5, 0;
	@%p16 bra 	BB0_3;

	mul.wide.s32 	%rd9, %r3, 16;
	add.s64 	%rd10, %rd1, %rd9;
	.loc 1 24 1
	st.global.v4.f32 	[%rd10], {%f5, %f6, %f7, %f8};
	bra.uni 	BB0_4;

BB0_3:
	mul.wide.s32 	%rd11, %r3, 8;
	add.s64 	%rd12, %rd1, %rd11;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f6;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f7;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f8;
	mov.b16 	%rs4, %temp;
}
	.loc 1 24 231
	st.global.v4.u16 	[%rd12], {%rs1, %rs2, %rs3, %rs4};

BB0_4:
	.loc 1 24 2
	ret;
}


