//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxKeyer.cu", 1399785249, 3071
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxKeyer(
	.param .u64 ShaderKernel_fxKeyer_param_0,
	.param .u32 ShaderKernel_fxKeyer_param_1,
	.param .u32 ShaderKernel_fxKeyer_param_2,
	.param .u32 ShaderKernel_fxKeyer_param_3,
	.param .u32 ShaderKernel_fxKeyer_param_4,
	.param .u64 ShaderKernel_fxKeyer_param_5,
	.param .u64 ShaderKernel_fxKeyer_param_6
)
{
	.reg .pred 	%p<13>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<94>;
	.reg .s64 	%rd<15>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local[64];

	ld.param.u64 	%rd4, [ShaderKernel_fxKeyer_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxKeyer_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxKeyer_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxKeyer_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxKeyer_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxKeyer_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 31 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 31 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 31 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 31 1
	cvt.rn.f32.s32	%f11, %r2;
	add.ftz.f32 	%f1, %f11, 0f3F000000;
	cvt.rn.f32.s32	%f12, %r3;
	add.ftz.f32 	%f2, %f12, 0f3F000000;
	.loc 1 31 1
	setp.gt.u32	%p4, %r1, 3;
	@%p4 bra 	BB0_3;

	.loc 1 31 1
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd2, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f13, %f14, %f15, %f16};

BB0_3:
	.loc 1 31 1
	bar.sync 	0;
	.loc 1 31 105
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 31 1
	setp.gt.ftz.f32	%p5, %f23, %f21;
	selp.f32	%f27, %f23, %f21, %p5;
	setp.gt.ftz.f32	%p6, %f23, %f22;
	selp.f32	%f28, %f23, %f22, %p6;
	.loc 1 31 1
	sub.ftz.f32 	%f29, %f22, %f27;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f30, %f29;
	.loc 1 31 1
	sub.ftz.f32 	%f31, %f21, %f28;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f32, %f31;
	.loc 1 31 1
	ld.shared.f32 	%f33, [ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local];
	setp.lt.ftz.f32	%p7, %f33, 0f00000000;
	selp.f32	%f34, %f30, %f32, %p7;
	ld.shared.f32 	%f35, [ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local+16];
	mul.ftz.f32 	%f36, %f34, %f35;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f37, %f36;
	mov.f32 	%f38, 0f3F800000;
	.loc 1 31 1
	sub.ftz.f32 	%f39, %f38, %f37;
	mul.ftz.f32 	%f40, %f39, 0f447A0000;
	fma.rn.ftz.f32 	%f41, %f37, 0f44FA0000, %f40;
	.loc 1 31 1
	setp.gt.ftz.f32	%p8, %f23, 0f3F7FDF3B;
	selp.f32	%f42, 0f3F7FDF3B, %f23, %p8;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f43, %f42;
	.loc 1 31 1
	setp.gt.ftz.f32	%p9, %f22, 0f3F7FDF3B;
	selp.f32	%f44, 0f3F7FDF3B, %f22, %p9;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f45, %f44;
	.loc 1 31 1
	setp.gt.ftz.f32	%p10, %f21, 0f3F7FDF3B;
	selp.f32	%f46, 0f3F7FDF3B, %f21, %p10;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f47, %f46;
	.loc 2 2740 10
	cvt.rmi.ftz.f32.f32	%f48, %f41;
	.loc 1 31 1
	add.ftz.f32 	%f49, %f48, %f43;
	add.ftz.f32 	%f50, %f48, %f45;
	add.ftz.f32 	%f51, %f48, %f47;
	.loc 1 31 1
	setp.gt.ftz.f32	%p11, %f37, 0f80000000;
	selp.f32	%f52, %f49, %f23, %p11;
	selp.f32	%f53, %f50, %f22, %p11;
	selp.f32	%f54, %f51, %f21, %p11;
	.loc 1 31 1
	mul.ftz.f32 	%f55, %f23, %f39;
	mul.ftz.f32 	%f56, %f22, %f39;
	mul.ftz.f32 	%f57, %f21, %f39;
	.loc 1 31 1
	ld.shared.v4.f32 	{%f58, %f59, %f60, %f61}, [ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local+48];
	.loc 1 31 1
	sub.ftz.f32 	%f63, %f38, %f58;
	mul.ftz.f32 	%f64, %f63, %f23;
	fma.rn.ftz.f32 	%f65, %f58, %f55, %f64;
	sub.ftz.f32 	%f67, %f38, %f59;
	mul.ftz.f32 	%f68, %f67, %f22;
	fma.rn.ftz.f32 	%f69, %f59, %f56, %f68;
	sub.ftz.f32 	%f71, %f38, %f60;
	mul.ftz.f32 	%f72, %f71, %f21;
	fma.rn.ftz.f32 	%f73, %f60, %f57, %f72;
	sub.ftz.f32 	%f75, %f38, %f61;
	mul.ftz.f32 	%f76, %f75, %f39;
	fma.rn.ftz.f32 	%f77, %f61, %f24, %f76;
	.loc 1 31 1
	ld.shared.v4.f32 	{%f78, %f79, %f80, %f81}, [ShaderKernel_fxKeyer$__cuda_local_var_170269_467_non_const_p_local+32];
	.loc 1 31 1
	sub.ftz.f32 	%f83, %f38, %f78;
	mul.ftz.f32 	%f84, %f83, %f65;
	fma.rn.ftz.f32 	%f3, %f78, %f52, %f84;
	sub.ftz.f32 	%f86, %f38, %f79;
	mul.ftz.f32 	%f87, %f86, %f69;
	fma.rn.ftz.f32 	%f4, %f79, %f53, %f87;
	sub.ftz.f32 	%f89, %f38, %f80;
	mul.ftz.f32 	%f90, %f89, %f73;
	fma.rn.ftz.f32 	%f5, %f80, %f54, %f90;
	sub.ftz.f32 	%f92, %f38, %f81;
	mul.ftz.f32 	%f93, %f92, %f77;
	fma.rn.ftz.f32 	%f6, %f81, %f24, %f93;
	.loc 1 31 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 31 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 31 1
	setp.eq.s32	%p12, %r5, 0;
	@%p12 bra 	BB0_5;

	.loc 1 31 1
	shl.b64 	%rd11, %rd3, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f5, %f4, %f3, %f6};
	bra.uni 	BB0_6;

BB0_5:
	.loc 1 31 1
	shl.b64 	%rd13, %rd3, 3;
	add.s64 	%rd14, %rd1, %rd13;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f6;
	mov.b16 	%rs4, %temp;
}
	.loc 1 31 231
	st.global.v4.u16 	[%rd14], {%rs1, %rs2, %rs3, %rs4};

BB0_6:
	.loc 1 31 2
	ret;
}


