//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxEmboss.cu", 1399785249, 2616
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_fxEmboss$__cuda_local_var_170266_468_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxEmboss(
	.param .u64 ShaderKernel_fxEmboss_param_0,
	.param .u32 ShaderKernel_fxEmboss_param_1,
	.param .u32 ShaderKernel_fxEmboss_param_2,
	.param .u32 ShaderKernel_fxEmboss_param_3,
	.param .u32 ShaderKernel_fxEmboss_param_4,
	.param .u64 ShaderKernel_fxEmboss_param_5,
	.param .u64 ShaderKernel_fxEmboss_param_6
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<3>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<56>;
	.reg .s64 	%rd<16>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxEmboss$__cuda_local_var_170266_468_non_const_p_local[16];

	ld.param.u64 	%rd4, [ShaderKernel_fxEmboss_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxEmboss_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxEmboss_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxEmboss_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxEmboss_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxEmboss_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 28 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 28 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 28 1
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 28 1
	cvt.rn.f32.s32	%f9, %r2;
	add.ftz.f32 	%f1, %f9, 0f3F000000;
	cvt.rn.f32.s32	%f10, %r3;
	add.ftz.f32 	%f2, %f10, 0f3F000000;
	.loc 1 28 1
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	.loc 1 28 1
	ld.global.v4.f32 	{%f11, %f12, %f13, %f14}, [%rd2];
	st.shared.v4.f32 	[ShaderKernel_fxEmboss$__cuda_local_var_170266_468_non_const_p_local], {%f11, %f12, %f13, %f14};

BB0_3:
	.loc 1 28 1
	bar.sync 	0;
	.loc 1 28 111
	// inline asm
	tex.2d.v4.f32.f32 {%f19, %f20, %f21, %f22}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 28 1
	mul.ftz.f32 	%f37, %f21, 0fC0400000;
	mul.ftz.f32 	%f38, %f20, 0fC0400000;
	mul.ftz.f32 	%f39, %f19, 0fC0400000;
	.loc 1 28 1
	add.ftz.f32 	%f30, %f2, 0fBF800000;
	add.ftz.f32 	%f29, %f1, 0f00000000;
	.loc 1 28 111
	// inline asm
	tex.2d.v4.f32.f32 {%f25, %f26, %f27, %f28}, [texture0_RECT, {%f29, %f30}];
	// inline asm
	.loc 1 28 1
	fma.rn.ftz.f32 	%f40, %f27, 0f3FC00000, %f37;
	fma.rn.ftz.f32 	%f41, %f26, 0f3FC00000, %f38;
	fma.rn.ftz.f32 	%f42, %f25, 0f3FC00000, %f39;
	.loc 1 28 1
	add.ftz.f32 	%f36, %f2, 0f00000000;
	add.ftz.f32 	%f35, %f1, 0fBF800000;
	.loc 1 28 111
	// inline asm
	tex.2d.v4.f32.f32 {%f31, %f32, %f33, %f34}, [texture0_RECT, {%f35, %f36}];
	// inline asm
	.loc 1 28 1
	fma.rn.ftz.f32 	%f43, %f33, 0f3FC00000, %f40;
	fma.rn.ftz.f32 	%f44, %f32, 0f3FC00000, %f41;
	fma.rn.ftz.f32 	%f45, %f31, 0f3FC00000, %f42;
	.loc 1 28 1
	ld.shared.v4.f32 	{%f46, %f47, %f48, %f49}, [ShaderKernel_fxEmboss$__cuda_local_var_170266_468_non_const_p_local];
	.loc 1 28 1
	mul.ftz.f32 	%f51, %f44, %f47;
	fma.rn.ftz.f32 	%f53, %f43, %f46, %f51;
	fma.rn.ftz.f32 	%f55, %f45, %f48, %f53;
	.loc 1 28 1
	add.ftz.f32 	%f5, %f55, 0f3EAAAAAB;
	.loc 1 28 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 28 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 28 1
	setp.eq.s32	%p5, %r5, 0;
	@%p5 bra 	BB0_5;

	.loc 1 28 1
	shl.b64 	%rd12, %rd3, 4;
	add.s64 	%rd13, %rd1, %rd12;
	st.global.v4.f32 	[%rd13], {%f5, %f5, %f5, %f22};
	bra.uni 	BB0_6;

BB0_5:
	.loc 1 28 1
	shl.b64 	%rd14, %rd3, 3;
	add.s64 	%rd15, %rd1, %rd14;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs2, %temp;
}
	.loc 1 28 231
	st.global.v4.u16 	[%rd15], {%rs1, %rs1, %rs1, %rs2};

BB0_6:
	.loc 1 28 2
	ret;
}


