//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxDay2NiteV.cu", 1399785249, 4459
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\iridas\\iridaslib\\gpu\\IrGPGPUShaders.h", 1399785249, 44561
	.file	3 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
.global .texref texture1_RECT;
// ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .func  (.param .b32 func_retval0) _Z5POWs_ff(
	.param .b32 _Z5POWs_ff_param_0,
	.param .b32 _Z5POWs_ff_param_1
)
{
	.reg .pred 	%p<5>;
	.reg .f32 	%f<10>;


	ld.param.f32 	%f3, [_Z5POWs_ff_param_0];
	ld.param.f32 	%f4, [_Z5POWs_ff_param_1];
	.loc 2 978 1
	setp.eq.ftz.f32	%p1, %f3, 0f00000000;
	setp.eq.ftz.f32	%p2, %f4, 0f00000000;
	and.pred  	%p3, %p1, %p2;
	.loc 2 978 1
	@!%p3 bra 	BB0_2;
	bra.uni 	BB0_1;

BB0_1:
	mov.f32 	%f9, 0f7FFFFFFF;
	bra.uni 	BB0_5;

BB0_2:
	.loc 2 978 1
	setp.geu.ftz.f32	%p4, %f4, 0f00000000;
	@%p4 bra 	BB0_4;

	mov.f32 	%f9, 0f3F800000;
	bra.uni 	BB0_5;

BB0_4:
	.loc 3 3600 10
	lg2.approx.ftz.f32 	%f5, %f3;
	mul.ftz.f32 	%f6, %f5, %f4;
	ex2.approx.ftz.f32 	%f9, %f6;

BB0_5:
	st.param.f32	[func_retval0+0], %f9;
	.loc 2 978 38
	ret;
}

.visible .entry ShaderKernel_fxDay2NiteV(
	.param .u64 ShaderKernel_fxDay2NiteV_param_0,
	.param .u32 ShaderKernel_fxDay2NiteV_param_1,
	.param .u32 ShaderKernel_fxDay2NiteV_param_2,
	.param .u32 ShaderKernel_fxDay2NiteV_param_3,
	.param .u32 ShaderKernel_fxDay2NiteV_param_4,
	.param .u64 ShaderKernel_fxDay2NiteV_param_5,
	.param .u64 ShaderKernel_fxDay2NiteV_param_6,
	.param .u64 ShaderKernel_fxDay2NiteV_param_7
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<194>;
	.reg .s64 	%rd<40>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local[112];

	ld.param.u64 	%rd4, [ShaderKernel_fxDay2NiteV_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxDay2NiteV_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxDay2NiteV_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxDay2NiteV_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxDay2NiteV_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxDay2NiteV_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 34 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 34 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 34 1
	@!%p3 bra 	BB1_6;
	bra.uni 	BB1_1;

BB1_1:
	.loc 1 34 1
	cvt.rn.f32.s32	%f11, %r2;
	add.ftz.f32 	%f1, %f11, 0f3F000000;
	cvt.rn.f32.s32	%f12, %r3;
	add.ftz.f32 	%f2, %f12, 0f3F000000;
	.loc 1 34 1
	setp.gt.u32	%p4, %r1, 6;
	@%p4 bra 	BB1_3;

	.loc 1 34 1
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd2, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f13, %f14, %f15, %f16};

BB1_3:
	.loc 1 34 1
	bar.sync 	0;
	.loc 1 34 111
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 34 1
	add.ftz.f32 	%f91, %f1, 0f00000000;
	add.ftz.f32 	%f98, %f2, 0fBF800000;
	.loc 1 34 111
	// inline asm
	tex.2d.v4.f32.f32 {%f27, %f28, %f29, %f30}, [texture0_RECT, {%f91, %f98}];
	// inline asm
	.loc 1 34 1
	ld.shared.v2.f32 	{%f99, %f100}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local];
	.loc 1 34 1
	fma.rn.ftz.f32 	%f102, %f29, %f99, %f23;
	fma.rn.ftz.f32 	%f104, %f28, %f100, %f22;
	.loc 1 34 1
	add.ftz.f32 	%f92, %f2, 0f3F800000;
	mov.f32 	%f105, 0f3F800000;
	.loc 1 34 111
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [texture0_RECT, {%f91, %f92}];
	// inline asm
	.loc 1 34 1
	fma.rn.ftz.f32 	%f106, %f35, %f99, %f102;
	fma.rn.ftz.f32 	%f107, %f34, %f100, %f104;
	.loc 1 34 1
	add.ftz.f32 	%f44, %f2, 0fC0000000;
	.loc 1 34 113
	// inline asm
	tex.2d.v4.f32.f32 {%f39, %f40, %f41, %f42}, [texture0_RECT, {%f91, %f44}];
	// inline asm
	.loc 1 34 1
	ld.shared.v2.f32 	{%f108, %f109}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local+16];
	.loc 1 34 1
	fma.rn.ftz.f32 	%f111, %f41, %f108, %f106;
	fma.rn.ftz.f32 	%f113, %f40, %f109, %f107;
	.loc 1 34 1
	add.ftz.f32 	%f50, %f2, 0f40000000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f45, %f46, %f47, %f48}, [texture0_RECT, {%f91, %f50}];
	// inline asm
	.loc 1 34 1
	fma.rn.ftz.f32 	%f114, %f47, %f108, %f111;
	fma.rn.ftz.f32 	%f115, %f46, %f109, %f113;
	.loc 1 34 1
	add.ftz.f32 	%f56, %f2, 0fC0400000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f51, %f52, %f53, %f54}, [texture0_RECT, {%f91, %f56}];
	// inline asm
	.loc 1 34 1
	ld.shared.v2.f32 	{%f116, %f117}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local+32];
	.loc 1 34 1
	fma.rn.ftz.f32 	%f119, %f53, %f116, %f114;
	fma.rn.ftz.f32 	%f121, %f52, %f117, %f115;
	.loc 1 34 1
	add.ftz.f32 	%f62, %f2, 0f40400000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f57, %f58, %f59, %f60}, [texture0_RECT, {%f91, %f62}];
	// inline asm
	.loc 1 34 1
	fma.rn.ftz.f32 	%f122, %f59, %f116, %f119;
	fma.rn.ftz.f32 	%f123, %f58, %f117, %f121;
	.loc 1 34 1
	add.ftz.f32 	%f68, %f2, 0fC0800000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f63, %f64, %f65, %f66}, [texture0_RECT, {%f91, %f68}];
	// inline asm
	.loc 1 34 1
	ld.shared.v2.f32 	{%f124, %f125}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local+48];
	.loc 1 34 1
	fma.rn.ftz.f32 	%f127, %f65, %f124, %f122;
	fma.rn.ftz.f32 	%f129, %f64, %f125, %f123;
	.loc 1 34 1
	add.ftz.f32 	%f74, %f2, 0f40800000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f69, %f70, %f71, %f72}, [texture0_RECT, {%f91, %f74}];
	// inline asm
	.loc 1 34 1
	fma.rn.ftz.f32 	%f130, %f71, %f124, %f127;
	fma.rn.ftz.f32 	%f131, %f70, %f125, %f129;
	.loc 1 34 1
	ld.shared.v2.f32 	{%f132, %f133}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local+64];
	.loc 1 34 1
	mul.ftz.f32 	%f135, %f130, %f132;
	mul.ftz.f32 	%f137, %f131, %f133;
	.loc 1 34 1
	sub.ftz.f32 	%f138, %f135, %f137;
	.loc 3 2910 10
	div.rn.ftz.f32 	%f139, %f105, %f138;
	.loc 1 34 1
	setp.gt.ftz.f32	%p5, %f138, 0f3A83126F;
	selp.f32	%f140, %f138, 0f3A83126F, %p5;
	.loc 3 3600 10
	lg2.approx.ftz.f32 	%f141, %f140;
	mul.ftz.f32 	%f142, %f141, 0f3F4CCCCD;
	ex2.approx.ftz.f32 	%f143, %f142;
	.loc 1 34 1
	mul.ftz.f32 	%f144, %f139, %f143;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f145, %f144;
	.loc 1 34 1
	sub.ftz.f32 	%f146, %f105, %f145;
	mul.ftz.f32 	%f147, %f146, %f137;
	fma.rn.ftz.f32 	%f148, %f145, %f135, %f147;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f75, %f76, %f77, %f78}, [texture1_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 34 1
	add.ftz.f32 	%f86, %f2, 0f00000000;
	add.ftz.f32 	%f85, %f1, 0fBF800000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f81, %f82, %f83, %f84}, [texture1_RECT, {%f85, %f86}];
	// inline asm
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f87, %f88, %f89, %f90}, [texture1_RECT, {%f91, %f92}];
	// inline asm
	.loc 1 34 1
	add.ftz.f32 	%f97, %f1, 0f3F800000;
	.loc 1 34 119
	// inline asm
	tex.2d.v4.f32.f32 {%f93, %f94, %f95, %f96}, [texture1_RECT, {%f97, %f98}];
	// inline asm
	.loc 1 34 1
	add.ftz.f32 	%f149, %f83, %f77;
	add.ftz.f32 	%f150, %f82, %f76;
	add.ftz.f32 	%f151, %f81, %f75;
	.loc 1 34 1
	add.ftz.f32 	%f152, %f149, %f89;
	add.ftz.f32 	%f153, %f150, %f88;
	add.ftz.f32 	%f154, %f151, %f87;
	.loc 1 34 1
	add.ftz.f32 	%f155, %f152, %f95;
	add.ftz.f32 	%f156, %f153, %f94;
	add.ftz.f32 	%f157, %f154, %f93;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f158, %f159, %f160, %f161}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local+80];
	.loc 1 34 1
	mul.ftz.f32 	%f163, %f148, %f158;
	mul.ftz.f32 	%f165, %f148, %f159;
	mul.ftz.f32 	%f167, %f148, %f160;
	mul.ftz.f32 	%f169, %f148, %f161;
	.loc 1 34 1
	mul.ftz.f32 	%f170, %f156, 0f3E1645A2;
	fma.rn.ftz.f32 	%f171, %f155, 0f3D991687, %f170;
	fma.rn.ftz.f32 	%f172, %f157, 0f3CE978D5, %f171;
	.loc 1 34 1
	ld.shared.v4.f32 	{%f173, %f174, %f175, %f176}, [ShaderKernel_fxDay2NiteV$__cuda_local_var_170272_636_non_const_p_local+96];
	.loc 1 34 1
	add.ftz.f32 	%f178, %f172, %f173;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f179, %f178;
	.loc 1 34 1
	add.ftz.f32 	%f181, %f172, %f174;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f182, %f181;
	.loc 1 34 1
	add.ftz.f32 	%f184, %f172, %f175;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f185, %f184;
	.loc 1 34 1
	sub.ftz.f32 	%f186, %f105, %f179;
	mul.ftz.f32 	%f187, %f186, %f163;
	fma.rn.ftz.f32 	%f3, %f179, %f77, %f187;
	sub.ftz.f32 	%f188, %f105, %f182;
	mul.ftz.f32 	%f189, %f188, %f165;
	fma.rn.ftz.f32 	%f4, %f182, %f76, %f189;
	sub.ftz.f32 	%f190, %f105, %f185;
	mul.ftz.f32 	%f191, %f190, %f167;
	fma.rn.ftz.f32 	%f5, %f185, %f75, %f191;
	sub.ftz.f32 	%f192, %f105, 0f3F800000;
	mul.ftz.f32 	%f193, %f192, %f169;
	fma.rn.ftz.f32 	%f6, %f78, 0f3F800000, %f193;
	.loc 1 34 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 34 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 34 1
	setp.eq.s32	%p6, %r5, 0;
	@%p6 bra 	BB1_5;

	.loc 1 34 1
	shl.b64 	%rd36, %rd3, 4;
	add.s64 	%rd37, %rd1, %rd36;
	st.global.v4.f32 	[%rd37], {%f5, %f4, %f3, %f6};
	bra.uni 	BB1_6;

BB1_5:
	.loc 1 34 1
	shl.b64 	%rd38, %rd3, 3;
	add.s64 	%rd39, %rd1, %rd38;
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs1, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs2, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs3, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f6;
	mov.b16 	%rs4, %temp;
}
	.loc 1 34 241
	st.global.v4.u16 	[%rd39], {%rs1, %rs2, %rs3, %rs4};

BB1_6:
	.loc 1 34 2
	ret;
}


