//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/fxCopperplate.cu", 1399785249, 3845
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShaderKernel_fxCopperplate(
	.param .u64 ShaderKernel_fxCopperplate_param_0,
	.param .u32 ShaderKernel_fxCopperplate_param_1,
	.param .u32 ShaderKernel_fxCopperplate_param_2,
	.param .u32 ShaderKernel_fxCopperplate_param_3,
	.param .u32 ShaderKernel_fxCopperplate_param_4,
	.param .u64 ShaderKernel_fxCopperplate_param_5,
	.param .u64 ShaderKernel_fxCopperplate_param_6
)
{
	.reg .pred 	%p<10>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<135>;
	.reg .s64 	%rd<24>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local[80];

	ld.param.u64 	%rd4, [ShaderKernel_fxCopperplate_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxCopperplate_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxCopperplate_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxCopperplate_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxCopperplate_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_fxCopperplate_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd5;
	.loc 1 32 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 32 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 32 1
	@!%p3 bra 	BB0_10;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 32 1
	cvt.rn.f32.s32	%f18, %r2;
	add.ftz.f32 	%f1, %f18, 0f3F000000;
	cvt.rn.f32.s32	%f19, %r3;
	add.ftz.f32 	%f2, %f19, 0f3F000000;
	.loc 1 32 1
	setp.gt.u32	%p4, %r1, 4;
	@%p4 bra 	BB0_3;

	.loc 1 32 1
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd2, %rd6;
	ld.global.v4.f32 	{%f20, %f21, %f22, %f23}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f20, %f21, %f22, %f23};

BB0_3:
	.loc 1 32 1
	bar.sync 	0;
	.loc 1 32 1
	add.ftz.f32 	%f39, %f2, 0f00000000;
	add.ftz.f32 	%f32, %f1, 0f3F800000;
	mov.f32 	%f134, 0f3F800000;
	.loc 1 32 111
	// inline asm
	tex.2d.v4.f32.f32 {%f28, %f29, %f30, %f31}, [texture0_RECT, {%f32, %f39}];
	// inline asm
	.loc 1 32 1
	ld.shared.v4.f32 	{%f59, %f60, %f61, %f62}, [ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local+64];
	mul.ftz.f32 	%f64, %f29, %f60;
	fma.rn.ftz.f32 	%f66, %f30, %f59, %f64;
	fma.rn.ftz.f32 	%f68, %f28, %f61, %f66;
	.loc 1 32 1
	add.ftz.f32 	%f38, %f1, 0fBF800000;
	.loc 1 32 111
	// inline asm
	tex.2d.v4.f32.f32 {%f34, %f35, %f36, %f37}, [texture0_RECT, {%f38, %f39}];
	// inline asm
	.loc 1 32 1
	mul.ftz.f32 	%f69, %f35, %f60;
	fma.rn.ftz.f32 	%f70, %f36, %f59, %f69;
	fma.rn.ftz.f32 	%f71, %f34, %f61, %f70;
	sub.ftz.f32 	%f72, %f68, %f71;
	.loc 1 32 1
	add.ftz.f32 	%f45, %f2, 0f3F800000;
	add.ftz.f32 	%f50, %f1, 0f00000000;
	.loc 1 32 111
	// inline asm
	tex.2d.v4.f32.f32 {%f40, %f41, %f42, %f43}, [texture0_RECT, {%f50, %f45}];
	// inline asm
	.loc 1 32 1
	mul.ftz.f32 	%f73, %f41, %f60;
	fma.rn.ftz.f32 	%f74, %f42, %f59, %f73;
	fma.rn.ftz.f32 	%f75, %f40, %f61, %f74;
	.loc 1 32 1
	add.ftz.f32 	%f51, %f2, 0fBF800000;
	.loc 1 32 111
	// inline asm
	tex.2d.v4.f32.f32 {%f46, %f47, %f48, %f49}, [texture0_RECT, {%f50, %f51}];
	// inline asm
	.loc 1 32 1
	mul.ftz.f32 	%f76, %f47, %f60;
	fma.rn.ftz.f32 	%f77, %f48, %f59, %f76;
	fma.rn.ftz.f32 	%f78, %f46, %f61, %f77;
	sub.ftz.f32 	%f79, %f75, %f78;
	.loc 1 32 1
	mul.ftz.f32 	%f80, %f79, 0f00000000;
	sub.ftz.f32 	%f81, %f80, %f72;
	mul.ftz.f32 	%f82, %f72, 0f00000000;
	mul.ftz.f32 	%f83, %f79, 0f3F800000;
	sub.ftz.f32 	%f84, %f82, %f83;
	.loc 1 32 1
	mul.ftz.f32 	%f85, %f84, %f84;
	fma.rn.ftz.f32 	%f86, %f81, %f81, %f85;
	sub.ftz.f32 	%f87, %f134, 0f00000000;
	fma.rn.ftz.f32 	%f88, %f87, %f87, %f86;
	.loc 2 2775 10
	rsqrt.approx.ftz.f32 	%f89, %f88;
	.loc 1 32 1
	mul.ftz.f32 	%f90, %f81, %f89;
	mul.ftz.f32 	%f91, %f84, %f89;
	mul.ftz.f32 	%f92, %f87, %f89;
	.loc 1 32 119
	// inline asm
	tex.2d.v4.f32.f32 {%f52, %f53, %f54, %f55}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 32 1
	mul.ftz.f32 	%f93, %f53, %f60;
	fma.rn.ftz.f32 	%f94, %f54, %f59, %f93;
	fma.rn.ftz.f32 	%f95, %f52, %f61, %f94;
	.loc 1 32 1
	ld.shared.v4.f32 	{%f96, %f97, %f98, %f99}, [ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local+32];
	.loc 1 32 1
	mul.ftz.f32 	%f101, %f96, %f95;
	mul.ftz.f32 	%f103, %f97, %f95;
	mul.ftz.f32 	%f105, %f98, %f95;
	.loc 1 32 1
	ld.shared.v4.f32 	{%f106, %f107, %f108, %f109}, [ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local+16];
	.loc 1 32 1
	fma.rn.ftz.f32 	%f4, %f101, %f106, %f101;
	fma.rn.ftz.f32 	%f5, %f103, %f107, %f103;
	fma.rn.ftz.f32 	%f6, %f105, %f108, %f105;
	.loc 1 32 1
	mul.ftz.f32 	%f113, %f91, 0f00000000;
	fma.rn.ftz.f32 	%f114, %f90, 0f00000000, %f113;
	add.ftz.f32 	%f115, %f114, %f92;
	.loc 1 32 1
	add.ftz.f32 	%f116, %f115, %f115;
	.loc 1 32 1
	fma.rn.ftz.f32 	%f117, %f116, %f90, 0f80000000;
	fma.rn.ftz.f32 	%f118, %f116, %f91, 0f80000000;
	fma.rn.ftz.f32 	%f119, %f116, %f92, 0fBF800000;
	.loc 1 32 1
	mul.ftz.f32 	%f120, %f118, 0f3E895E9E;
	fma.rn.ftz.f32 	%f121, %f117, 0f3EB72DA1, %f120;
	fma.rn.ftz.f32 	%f122, %f119, 0f3F64F766, %f121;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f7, %f122;
	.loc 1 32 1
	setp.eq.ftz.f32	%p5, %f7, 0f00000000;
	.loc 1 32 1
	ld.shared.f32 	%f8, [ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local];
	.loc 1 32 1
	setp.eq.ftz.f32	%p6, %f8, 0f00000000;
	and.pred  	%p7, %p5, %p6;
	.loc 1 32 1
	@!%p7 bra 	BB0_5;
	bra.uni 	BB0_4;

BB0_4:
	mov.f32 	%f134, 0f7FFFFFFF;
	bra.uni 	BB0_7;

BB0_5:
	.loc 1 32 1
	setp.geu.ftz.f32	%p8, %f8, 0f00000000;
	@%p8 bra 	BB0_6;
	bra.uni 	BB0_7;

BB0_6:
	.loc 2 3600 10
	lg2.approx.ftz.f32 	%f123, %f7;
	mul.ftz.f32 	%f124, %f8, %f123;
	ex2.approx.ftz.f32 	%f134, %f124;

BB0_7:
	.loc 1 32 1
	ld.shared.v4.f32 	{%f127, %f128, %f129, %f130}, [ShaderKernel_fxCopperplate$__cuda_local_var_170270_473_non_const_p_local+48];
	.loc 1 32 1
	fma.rn.ftz.f32 	%f11, %f134, %f127, %f4;
	fma.rn.ftz.f32 	%f12, %f134, %f128, %f5;
	fma.rn.ftz.f32 	%f13, %f134, %f129, %f6;
	.loc 1 32 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 32 1
	cvt.s64.s32	%rd3, %r13;
	.loc 1 32 1
	setp.eq.s32	%p9, %r5, 0;
	@%p9 bra 	BB0_9;

	.loc 1 32 1
	shl.b64 	%rd20, %rd3, 4;
	add.s64 	%rd21, %rd1, %rd20;
	st.global.v4.f32 	[%rd21], {%f13, %f12, %f11, %f55};
	bra.uni 	BB0_10;

BB0_9:
	.loc 1 32 1
	shl.b64 	%rd22, %rd3, 3;
	add.s64 	%rd23, %rd1, %rd22;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f13;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f12;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f11;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f55;
	mov.b16 	%rs4, %temp;
}
	.loc 1 32 241
	st.global.v4.u16 	[%rd23], {%rs1, %rs2, %rs3, %rs4};

BB0_10:
	.loc 1 32 2
	ret;
}


