//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Effects/DirectionalBlur.cu", 1399785316, 3232
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref inSrcTexture;
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry ShearHorizontalKernel(
	.param .u64 ShearHorizontalKernel_param_0,
	.param .u32 ShearHorizontalKernel_param_1,
	.param .u64 ShearHorizontalKernel_param_2,
	.param .u32 ShearHorizontalKernel_param_3,
	.param .u32 ShearHorizontalKernel_param_4,
	.param .u32 ShearHorizontalKernel_param_5,
	.param .u32 ShearHorizontalKernel_param_6,
	.param .u32 ShearHorizontalKernel_param_7,
	.param .f32 ShearHorizontalKernel_param_8,
	.param .u32 ShearHorizontalKernel_param_9
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<17>;
	.reg .f32 	%f<47>;
	.reg .s64 	%rd<8>;


	ld.param.u32 	%r4, [ShearHorizontalKernel_param_1];
	ld.param.u64 	%rd2, [ShearHorizontalKernel_param_2];
	ld.param.u32 	%r7, [ShearHorizontalKernel_param_3];
	ld.param.u32 	%r8, [ShearHorizontalKernel_param_4];
	ld.param.u32 	%r5, [ShearHorizontalKernel_param_5];
	ld.param.u32 	%r6, [ShearHorizontalKernel_param_6];
	ld.param.f32 	%f19, [ShearHorizontalKernel_param_8];
	ld.param.u32 	%r9, [ShearHorizontalKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 24 1
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r10, %r11, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r13, %r14, %r15;
	cvt.rn.f32.s32	%f20, %r1;
	cvt.rn.f32.s32	%f1, %r2;
	mul.ftz.f32 	%f21, %f1, %f19;
	sub.ftz.f32 	%f22, %f20, %f21;
	cvt.rn.f32.s32	%f23, %r9;
	sub.ftz.f32 	%f2, %f22, %f23;
	.loc 1 24 1
	setp.lt.s32	%p1, %r1, %r7;
	setp.lt.s32	%p2, %r2, %r8;
	and.pred  	%p3, %p1, %p2;
	.loc 1 24 1
	mov.f32 	%f43, 0f00000000;
	mov.f32 	%f44, 0f00000000;
	mov.f32 	%f45, 0f00000000;
	mov.f32 	%f46, 0f00000000;
	.loc 1 24 1
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 24 1
	setp.ltu.ftz.f32	%p4, %f2, 0f00000000;
	@%p4 bra 	BB0_4;

	add.s32 	%r16, %r6, -1;
	cvt.rn.f32.s32	%f32, %r16;
	setp.gtu.ftz.f32	%p5, %f2, %f32;
	@%p5 bra 	BB0_4;

	.loc 1 24 1
	add.ftz.f32 	%f37, %f2, 0f00000000;
	.loc 1 24 251
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [inSrcTexture, {%f37, %f1}];
	// inline asm
	mov.f32 	%f46, %f36;
	mov.f32 	%f45, %f35;
	mov.f32 	%f44, %f34;
	mov.f32 	%f43, %f33;

BB0_4:
	.loc 1 24 1
	mad.lo.s32 	%r3, %r2, %r5, %r1;
	.loc 1 24 1
	setp.eq.s32	%p6, %r4, 0;
	@%p6 bra 	BB0_6;

	mul.wide.s32 	%rd4, %r3, 16;
	add.s64 	%rd5, %rd1, %rd4;
	.loc 1 24 1
	st.global.v4.f32 	[%rd5], {%f43, %f44, %f45, %f46};
	bra.uni 	BB0_7;

BB0_6:
	mul.wide.s32 	%rd6, %r3, 8;
	add.s64 	%rd7, %rd1, %rd6;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f43;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f44;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f45;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f46;
	mov.b16 	%rs4, %temp;
}
	.loc 1 24 223
	st.global.v4.u16 	[%rd7], {%rs1, %rs2, %rs3, %rs4};

BB0_7:
	.loc 1 24 2
	ret;
}

.visible .entry ShearVerticalKernel(
	.param .u64 ShearVerticalKernel_param_0,
	.param .u32 ShearVerticalKernel_param_1,
	.param .u64 ShearVerticalKernel_param_2,
	.param .u32 ShearVerticalKernel_param_3,
	.param .u32 ShearVerticalKernel_param_4,
	.param .u32 ShearVerticalKernel_param_5,
	.param .u32 ShearVerticalKernel_param_6,
	.param .u32 ShearVerticalKernel_param_7,
	.param .f32 ShearVerticalKernel_param_8,
	.param .u32 ShearVerticalKernel_param_9
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<17>;
	.reg .f32 	%f<47>;
	.reg .s64 	%rd<8>;


	ld.param.u32 	%r4, [ShearVerticalKernel_param_1];
	ld.param.u64 	%rd2, [ShearVerticalKernel_param_2];
	ld.param.u32 	%r7, [ShearVerticalKernel_param_3];
	ld.param.u32 	%r8, [ShearVerticalKernel_param_4];
	ld.param.u32 	%r5, [ShearVerticalKernel_param_5];
	ld.param.u32 	%r6, [ShearVerticalKernel_param_7];
	ld.param.f32 	%f19, [ShearVerticalKernel_param_8];
	ld.param.u32 	%r9, [ShearVerticalKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd2;
	.loc 1 24 1
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r10, %r11, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r13, %r14, %r15;
	cvt.rn.f32.s32	%f20, %r2;
	cvt.rn.f32.s32	%f1, %r1;
	mul.ftz.f32 	%f21, %f1, %f19;
	sub.ftz.f32 	%f22, %f20, %f21;
	cvt.rn.f32.s32	%f23, %r9;
	sub.ftz.f32 	%f2, %f22, %f23;
	.loc 1 24 1
	setp.lt.s32	%p1, %r1, %r7;
	setp.lt.s32	%p2, %r2, %r8;
	and.pred  	%p3, %p1, %p2;
	.loc 1 24 1
	mov.f32 	%f43, 0f00000000;
	mov.f32 	%f44, 0f00000000;
	mov.f32 	%f45, 0f00000000;
	mov.f32 	%f46, 0f00000000;
	.loc 1 24 1
	@!%p3 bra 	BB1_7;
	bra.uni 	BB1_1;

BB1_1:
	.loc 1 24 1
	setp.ltu.ftz.f32	%p4, %f2, 0f00000000;
	@%p4 bra 	BB1_4;

	add.s32 	%r16, %r6, -1;
	cvt.rn.f32.s32	%f32, %r16;
	setp.gtu.ftz.f32	%p5, %f2, %f32;
	@%p5 bra 	BB1_4;

	.loc 1 24 1
	add.ftz.f32 	%f37, %f1, 0f3F000000;
	add.ftz.f32 	%f38, %f2, 0f3F000000;
	.loc 1 24 254
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [inSrcTexture, {%f37, %f38}];
	// inline asm
	mov.f32 	%f46, %f36;
	mov.f32 	%f45, %f35;
	mov.f32 	%f44, %f34;
	mov.f32 	%f43, %f33;

BB1_4:
	.loc 1 24 1
	mad.lo.s32 	%r3, %r2, %r5, %r1;
	.loc 1 24 1
	setp.eq.s32	%p6, %r4, 0;
	@%p6 bra 	BB1_6;

	mul.wide.s32 	%rd4, %r3, 16;
	add.s64 	%rd5, %rd1, %rd4;
	.loc 1 24 1
	st.global.v4.f32 	[%rd5], {%f43, %f44, %f45, %f46};
	bra.uni 	BB1_7;

BB1_6:
	mul.wide.s32 	%rd6, %r3, 8;
	add.s64 	%rd7, %rd1, %rd6;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f43;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f44;
	mov.b16 	%rs2, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f45;
	mov.b16 	%rs3, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f46;
	mov.b16 	%rs4, %temp;
}
	.loc 1 24 232
	st.global.v4.u16 	[%rd7], {%rs1, %rs2, %rs3, %rs4};

BB1_7:
	.loc 1 24 2
	ret;
}


