//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/GPUFoundation/Src/ImageProcessing/Deinterlace.cu", 1399785311, 5921
	.file	2 "D:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\MediaCore\\GPUFoundation\\API\\Inc\\GPUFoundation/KernelSupport/PixelUtils.h", 1399785310, 5707
	.file	3 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref ioBufTexture;
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .func  (.param .align 16 .b8 func_retval0[16]) _Z18UnpremultiplyPixel8PixelRGB(
	.param .align 16 .b8 _Z18UnpremultiplyPixel8PixelRGB_param_0[16]
)
{
	.reg .pred 	%p<2>;
	.reg .f32 	%f<24>;


	ld.param.f32 	%f3, [_Z18UnpremultiplyPixel8PixelRGB_param_0+8];
	ld.param.f32 	%f2, [_Z18UnpremultiplyPixel8PixelRGB_param_0+4];
	ld.param.f32 	%f1, [_Z18UnpremultiplyPixel8PixelRGB_param_0];
	ld.param.f32 	%f12, [_Z18UnpremultiplyPixel8PixelRGB_param_0+12];
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f20, %f12;
	.loc 2 45 1
	add.ftz.f32 	%f13, %f20, 0fB70637BD;
	setp.gtu.ftz.f32	%p1, %f13, 0f00000000;
	@%p1 bra 	BB0_2;

	mov.f32 	%f23, 0f00000000;
	mov.f32 	%f22, %f23;
	mov.f32 	%f21, %f23;
	mov.f32 	%f20, %f23;
	bra.uni 	BB0_3;

BB0_2:
	mov.f32 	%f18, 0f3F800000;
	.loc 3 3606 10
	div.approx.ftz.f32 	%f19, %f18, %f20;
	.loc 2 45 1
	mul.ftz.f32 	%f21, %f3, %f19;
	mul.ftz.f32 	%f22, %f2, %f19;
	mul.ftz.f32 	%f23, %f1, %f19;

BB0_3:
	st.param.f32	[func_retval0+0], %f23;
	st.param.f32	[func_retval0+4], %f22;
	st.param.f32	[func_retval0+8], %f21;
	st.param.f32	[func_retval0+12], %f20;
	.loc 2 45 1
	ret;
}

.visible .entry DeinterlaceSamplerKernel(
	.param .u64 DeinterlaceSamplerKernel_param_0,
	.param .u64 DeinterlaceSamplerKernel_param_1,
	.param .u32 DeinterlaceSamplerKernel_param_2,
	.param .u32 DeinterlaceSamplerKernel_param_3,
	.param .u32 DeinterlaceSamplerKernel_param_4,
	.param .u32 DeinterlaceSamplerKernel_param_5,
	.param .u32 DeinterlaceSamplerKernel_param_6
)
{
	.reg .pred 	%p<68>;
	.reg .s16 	%rs<17>;
	.reg .s32 	%r<70>;
	.reg .f32 	%f<252>;
	.reg .s64 	%rd<37>;


	ld.param.u64 	%rd4, [DeinterlaceSamplerKernel_param_1];
	ld.param.u32 	%r3, [DeinterlaceSamplerKernel_param_2];
	ld.param.u32 	%r4, [DeinterlaceSamplerKernel_param_3];
	ld.param.u32 	%r5, [DeinterlaceSamplerKernel_param_4];
	ld.param.u32 	%r6, [DeinterlaceSamplerKernel_param_5];
	ld.param.u32 	%r7, [DeinterlaceSamplerKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd4;
	.loc 1 43 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r14, %r11, %r12, %r13;
	shl.b32 	%r15, %r14, 1;
	.loc 1 43 1
	setp.ne.s32	%p2, %r7, 0;
	selp.u32	%r16, 1, 0, %p2;
	add.s32 	%r2, %r15, %r16;
	.loc 1 43 1
	setp.ge.s32	%p3, %r1, %r5;
	@%p3 bra 	BB1_65;

	.loc 1 43 1
	setp.gt.s32	%p4, %r2, 0;
	add.s32 	%r17, %r2, 1;
	setp.lt.s32	%p5, %r17, %r6;
	and.pred  	%p1, %p4, %p5;
	setp.gt.s32	%p6, %r1, 0;
	and.pred  	%p7, %p1, %p6;
	.loc 1 43 1
	add.s32 	%r18, %r1, 1;
	setp.lt.s32	%p8, %r18, %r5;
	and.pred  	%p9, %p7, %p8;
	.loc 1 43 1
	mad.lo.s32 	%r19, %r2, %r3, %r1;
	mul.wide.s32 	%rd5, %r19, 16;
	add.s64 	%rd2, %rd1, %rd5;
	mul.wide.s32 	%rd6, %r19, 8;
	add.s64 	%rd3, %rd1, %rd6;
	.loc 1 43 1
	@%p9 bra 	BB1_37;

	.loc 1 43 1
	@%p1 bra 	BB1_11;

	or.b32  	%r20, %r2, %r7;
	setp.eq.s32	%p10, %r20, 0;
	.loc 1 43 1
	@%p10 bra 	BB1_8;

	.loc 1 43 1
	add.s32 	%r21, %r6, -1;
	setp.eq.s32	%p12, %r2, %r21;
	and.pred  	%p13, %p12, %p2;
	@!%p13 bra 	BB1_65;
	bra.uni 	BB1_5;

BB1_5:
	.loc 1 43 1
	cvt.rn.f32.s32	%f129, %r1;
	add.ftz.f32 	%f127, %f129, 0f3F000000;
	cvt.rn.f32.s32	%f130, %r2;
	add.ftz.f32 	%f128, %f130, 0fBF000000;
	.loc 1 43 228
	// inline asm
	tex.2d.v4.f32.f32 {%f123, %f124, %f125, %f126}, [ioBufTexture, {%f127, %f128}];
	// inline asm
	.loc 1 43 1
	setp.eq.s32	%p14, %r4, 0;
	@%p14 bra 	BB1_7;

	.loc 1 43 1
	st.global.v4.f32 	[%rd2], {%f123, %f124, %f125, %f126};
	bra.uni 	BB1_65;

BB1_7:
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f123;
	mov.b16 	%rs1, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f124;
	mov.b16 	%rs2, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f125;
	mov.b16 	%rs3, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f126;
	mov.b16 	%rs4, %temp;
}
	.loc 1 43 231
	st.global.v4.u16 	[%rd3], {%rs1, %rs2, %rs3, %rs4};
	bra.uni 	BB1_65;

BB1_8:
	.loc 1 43 1
	cvt.rn.f32.s32	%f137, %r1;
	add.ftz.f32 	%f135, %f137, 0f3F000000;
	mov.f32 	%f136, 0f3FC00000;
	.loc 1 43 141
	// inline asm
	tex.2d.v4.f32.f32 {%f131, %f132, %f133, %f134}, [ioBufTexture, {%f135, %f136}];
	// inline asm
	.loc 1 43 1
	setp.eq.s32	%p15, %r4, 0;
	@%p15 bra 	BB1_10;

	.loc 1 43 1
	st.global.v4.f32 	[%rd2], {%f131, %f132, %f133, %f134};
	bra.uni 	BB1_65;

BB1_10:
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f131;
	mov.b16 	%rs5, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f132;
	mov.b16 	%rs6, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f133;
	mov.b16 	%rs7, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f134;
	mov.b16 	%rs8, %temp;
}
	.loc 1 43 231
	st.global.v4.u16 	[%rd3], {%rs5, %rs6, %rs7, %rs8};
	bra.uni 	BB1_65;

BB1_11:
	.loc 1 43 1
	cvt.rn.f32.s32	%f150, %r1;
	add.ftz.f32 	%f148, %f150, 0f3F000000;
	cvt.rn.f32.s32	%f151, %r2;
	add.ftz.f32 	%f143, %f151, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f138, %f139, %f140, %f141}, [ioBufTexture, {%f148, %f143}];
	// inline asm
	mul.ftz.f32 	%f18, %f140, %f141;
	mul.ftz.f32 	%f19, %f139, %f141;
	mul.ftz.f32 	%f20, %f138, %f141;
	.loc 1 43 1
	add.ftz.f32 	%f149, %f151, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f144, %f145, %f146, %f147}, [ioBufTexture, {%f148, %f149}];
	// inline asm
	mul.ftz.f32 	%f230, %f146, %f147;
	mul.ftz.f32 	%f229, %f145, %f147;
	mul.ftz.f32 	%f228, %f144, %f147;
	.loc 1 43 1
	add.ftz.f32 	%f152, %f20, %f228;
	mul.ftz.f32 	%f25, %f152, 0f3F000000;
	add.ftz.f32 	%f153, %f19, %f229;
	mul.ftz.f32 	%f26, %f153, 0f3F000000;
	add.ftz.f32 	%f154, %f18, %f230;
	mul.ftz.f32 	%f27, %f154, 0f3F000000;
	add.ftz.f32 	%f155, %f141, %f147;
	mul.ftz.f32 	%f28, %f155, 0f3F000000;
	setp.gt.ftz.f32	%p16, %f20, %f228;
	mov.f32 	%f231, %f147;
	.loc 1 43 1
	@%p16 bra 	BB1_14;

	setp.gt.ftz.f32	%p17, %f25, %f228;
	@%p17 bra 	BB1_16;

	setp.gt.ftz.f32	%p18, %f20, %f25;
	selp.f32	%f228, %f20, %f25, %p18;
	bra.uni 	BB1_16;

BB1_14:
	.loc 1 43 1
	setp.gt.ftz.f32	%p19, %f228, %f25;
	@%p19 bra 	BB1_16;

	setp.gt.ftz.f32	%p20, %f20, %f25;
	selp.f32	%f228, %f25, %f20, %p20;

BB1_16:
	setp.gt.ftz.f32	%p21, %f19, %f229;
	@%p21 bra 	BB1_19;

	setp.gt.ftz.f32	%p22, %f26, %f229;
	@%p22 bra 	BB1_21;

	setp.gt.ftz.f32	%p23, %f19, %f26;
	selp.f32	%f229, %f19, %f26, %p23;
	bra.uni 	BB1_21;

BB1_19:
	.loc 1 43 1
	setp.gt.ftz.f32	%p24, %f229, %f26;
	@%p24 bra 	BB1_21;

	setp.gt.ftz.f32	%p25, %f19, %f26;
	selp.f32	%f229, %f26, %f19, %p25;

BB1_21:
	setp.gt.ftz.f32	%p26, %f18, %f230;
	@%p26 bra 	BB1_24;

	setp.gt.ftz.f32	%p27, %f27, %f230;
	@%p27 bra 	BB1_26;

	setp.gt.ftz.f32	%p28, %f18, %f27;
	selp.f32	%f230, %f18, %f27, %p28;
	bra.uni 	BB1_26;

BB1_24:
	.loc 1 43 1
	setp.gt.ftz.f32	%p29, %f230, %f27;
	@%p29 bra 	BB1_26;

	setp.gt.ftz.f32	%p30, %f18, %f27;
	selp.f32	%f230, %f27, %f18, %p30;

BB1_26:
	setp.gt.ftz.f32	%p31, %f141, %f147;
	@%p31 bra 	BB1_29;

	setp.gt.ftz.f32	%p32, %f28, %f147;
	@%p32 bra 	BB1_31;

	setp.gt.ftz.f32	%p33, %f141, %f28;
	selp.f32	%f231, %f141, %f28, %p33;
	bra.uni 	BB1_31;

BB1_29:
	.loc 1 43 1
	setp.gt.ftz.f32	%p34, %f147, %f28;
	@%p34 bra 	BB1_31;

	setp.gt.ftz.f32	%p35, %f141, %f28;
	selp.f32	%f231, %f28, %f141, %p35;

BB1_31:
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f235, %f231;
	.loc 2 45 1
	add.ftz.f32 	%f156, %f235, 0fB70637BD;
	setp.gtu.ftz.f32	%p36, %f156, 0f00000000;
	@%p36 bra 	BB1_33;

	mov.f32 	%f235, 0f00000000;
	mov.f32 	%f234, %f235;
	mov.f32 	%f233, %f235;
	mov.f32 	%f232, %f235;
	bra.uni 	BB1_34;

BB1_33:
	mov.f32 	%f161, 0f3F800000;
	.loc 3 3606 10
	div.approx.ftz.f32 	%f162, %f161, %f235;
	.loc 2 45 1
	mul.ftz.f32 	%f234, %f230, %f162;
	mul.ftz.f32 	%f233, %f229, %f162;
	mul.ftz.f32 	%f232, %f228, %f162;

BB1_34:
	.loc 1 43 1
	setp.eq.s32	%p37, %r4, 0;
	@%p37 bra 	BB1_36;

	mul.wide.s32 	%rd14, %r19, 16;
	add.s64 	%rd15, %rd1, %rd14;
	.loc 1 43 1
	st.global.v4.f32 	[%rd15], {%f232, %f233, %f234, %f235};
	bra.uni 	BB1_65;

BB1_36:
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f232;
	mov.b16 	%rs9, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f233;
	mov.b16 	%rs10, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f234;
	mov.b16 	%rs11, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f235;
	mov.b16 	%rs12, %temp;
}
	mul.wide.s32 	%rd17, %r19, 8;
	add.s64 	%rd18, %rd1, %rd17;
	.loc 1 43 241
	st.global.v4.u16 	[%rd18], {%rs9, %rs10, %rs11, %rs12};
	bra.uni 	BB1_65;

BB1_37:
	.loc 1 43 1
	cvt.rn.f32.s32	%f199, %r1;
	add.ftz.f32 	%f185, %f199, 0fBF000000;
	cvt.rn.f32.s32	%f200, %r2;
	add.ftz.f32 	%f180, %f200, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f163, %f164, %f165, %f166}, [ioBufTexture, {%f185, %f180}];
	// inline asm
	mul.ftz.f32 	%f238, %f165, %f166;
	mul.ftz.f32 	%f237, %f164, %f166;
	mul.ftz.f32 	%f236, %f163, %f166;
	.loc 1 43 1
	add.ftz.f32 	%f191, %f199, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f169, %f170, %f171, %f172}, [ioBufTexture, {%f191, %f180}];
	// inline asm
	mul.ftz.f32 	%f58, %f171, %f172;
	mul.ftz.f32 	%f59, %f170, %f172;
	mul.ftz.f32 	%f60, %f169, %f172;
	.loc 1 43 1
	add.ftz.f32 	%f197, %f199, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f175, %f176, %f177, %f178}, [ioBufTexture, {%f197, %f180}];
	// inline asm
	mul.ftz.f32 	%f63, %f177, %f178;
	mul.ftz.f32 	%f62, %f176, %f178;
	mul.ftz.f32 	%f61, %f175, %f178;
	.loc 1 43 1
	add.ftz.f32 	%f198, %f200, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f181, %f182, %f183, %f184}, [ioBufTexture, {%f185, %f198}];
	// inline asm
	mul.ftz.f32 	%f67, %f183, %f184;
	mul.ftz.f32 	%f66, %f182, %f184;
	mul.ftz.f32 	%f65, %f181, %f184;
	// inline asm
	tex.2d.v4.f32.f32 {%f187, %f188, %f189, %f190}, [ioBufTexture, {%f191, %f198}];
	// inline asm
	mul.ftz.f32 	%f246, %f189, %f190;
	mul.ftz.f32 	%f245, %f188, %f190;
	mul.ftz.f32 	%f244, %f187, %f190;
	// inline asm
	tex.2d.v4.f32.f32 {%f193, %f194, %f195, %f196}, [ioBufTexture, {%f197, %f198}];
	// inline asm
	mul.ftz.f32 	%f242, %f195, %f196;
	mul.ftz.f32 	%f241, %f194, %f196;
	mul.ftz.f32 	%f240, %f193, %f196;
	.loc 1 43 1
	sub.ftz.f32 	%f201, %f236, %f240;
	sub.ftz.f32 	%f202, %f237, %f241;
	sub.ftz.f32 	%f203, %f238, %f242;
	mul.ftz.f32 	%f204, %f202, %f202;
	fma.rn.ftz.f32 	%f205, %f203, %f203, %f204;
	fma.rn.ftz.f32 	%f206, %f201, %f201, %f205;
	sub.ftz.f32 	%f207, %f60, %f244;
	sub.ftz.f32 	%f208, %f59, %f245;
	sub.ftz.f32 	%f209, %f58, %f246;
	mul.ftz.f32 	%f210, %f208, %f208;
	fma.rn.ftz.f32 	%f211, %f209, %f209, %f210;
	fma.rn.ftz.f32 	%f77, %f207, %f207, %f211;
	sub.ftz.f32 	%f212, %f61, %f65;
	sub.ftz.f32 	%f213, %f62, %f66;
	sub.ftz.f32 	%f214, %f63, %f67;
	mul.ftz.f32 	%f215, %f213, %f213;
	fma.rn.ftz.f32 	%f216, %f214, %f214, %f215;
	fma.rn.ftz.f32 	%f78, %f212, %f212, %f216;
	.loc 1 43 1
	setp.lt.ftz.f32	%p40, %f206, %f77;
	setp.lt.ftz.f32	%p41, %f206, %f78;
	and.pred  	%p42, %p40, %p41;
	mov.f32 	%f243, %f196;
	mov.f32 	%f239, %f166;
	mov.f32 	%f247, %f190;
	.loc 1 43 1
	@%p42 bra 	BB1_39;

	.loc 1 43 1
	setp.lt.ftz.f32	%p43, %f77, %f78;
	.loc 1 43 1
	selp.f32	%f237, %f59, %f62, %p43;
	selp.f32	%f236, %f60, %f61, %p43;
	selp.f32	%f238, %f58, %f63, %p43;
	selp.f32	%f239, %f172, %f178, %p43;
	selp.f32	%f241, %f245, %f66, %p43;
	selp.f32	%f240, %f244, %f65, %p43;
	selp.f32	%f242, %f246, %f67, %p43;
	selp.f32	%f243, %f190, %f184, %p43;

BB1_39:
	.loc 1 43 1
	add.ftz.f32 	%f217, %f236, %f240;
	mul.ftz.f32 	%f95, %f217, 0f3F000000;
	add.ftz.f32 	%f218, %f237, %f241;
	mul.ftz.f32 	%f96, %f218, 0f3F000000;
	add.ftz.f32 	%f219, %f238, %f242;
	mul.ftz.f32 	%f97, %f219, 0f3F000000;
	add.ftz.f32 	%f220, %f239, %f243;
	mul.ftz.f32 	%f98, %f220, 0f3F000000;
	setp.gt.ftz.f32	%p44, %f60, %f244;
	@%p44 bra 	BB1_42;

	setp.gt.ftz.f32	%p45, %f95, %f244;
	@%p45 bra 	BB1_44;

	setp.gt.ftz.f32	%p46, %f60, %f95;
	selp.f32	%f244, %f60, %f95, %p46;
	bra.uni 	BB1_44;

BB1_42:
	.loc 1 43 1
	setp.gt.ftz.f32	%p47, %f244, %f95;
	@%p47 bra 	BB1_44;

	setp.gt.ftz.f32	%p48, %f60, %f95;
	selp.f32	%f244, %f95, %f60, %p48;

BB1_44:
	setp.gt.ftz.f32	%p49, %f59, %f245;
	@%p49 bra 	BB1_47;

	setp.gt.ftz.f32	%p50, %f96, %f245;
	@%p50 bra 	BB1_49;

	setp.gt.ftz.f32	%p51, %f59, %f96;
	selp.f32	%f245, %f59, %f96, %p51;
	bra.uni 	BB1_49;

BB1_47:
	.loc 1 43 1
	setp.gt.ftz.f32	%p52, %f245, %f96;
	@%p52 bra 	BB1_49;

	setp.gt.ftz.f32	%p53, %f59, %f96;
	selp.f32	%f245, %f96, %f59, %p53;

BB1_49:
	setp.gt.ftz.f32	%p54, %f58, %f246;
	@%p54 bra 	BB1_52;

	setp.gt.ftz.f32	%p55, %f97, %f246;
	@%p55 bra 	BB1_54;

	setp.gt.ftz.f32	%p56, %f58, %f97;
	selp.f32	%f246, %f58, %f97, %p56;
	bra.uni 	BB1_54;

BB1_52:
	.loc 1 43 1
	setp.gt.ftz.f32	%p57, %f246, %f97;
	@%p57 bra 	BB1_54;

	setp.gt.ftz.f32	%p58, %f58, %f97;
	selp.f32	%f246, %f97, %f58, %p58;

BB1_54:
	setp.gt.ftz.f32	%p59, %f172, %f190;
	@%p59 bra 	BB1_57;

	setp.gt.ftz.f32	%p60, %f98, %f190;
	@%p60 bra 	BB1_59;

	setp.gt.ftz.f32	%p61, %f172, %f98;
	selp.f32	%f247, %f172, %f98, %p61;
	bra.uni 	BB1_59;

BB1_57:
	.loc 1 43 1
	setp.gt.ftz.f32	%p62, %f190, %f98;
	@%p62 bra 	BB1_59;

	setp.gt.ftz.f32	%p63, %f172, %f98;
	selp.f32	%f247, %f98, %f172, %p63;

BB1_59:
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f251, %f247;
	.loc 2 45 1
	add.ftz.f32 	%f221, %f251, 0fB70637BD;
	setp.gtu.ftz.f32	%p64, %f221, 0f00000000;
	@%p64 bra 	BB1_61;

	mov.f32 	%f251, 0f00000000;
	mov.f32 	%f250, %f251;
	mov.f32 	%f249, %f251;
	mov.f32 	%f248, %f251;
	bra.uni 	BB1_62;

BB1_61:
	mov.f32 	%f226, 0f3F800000;
	.loc 3 3606 10
	div.approx.ftz.f32 	%f227, %f226, %f251;
	.loc 2 45 1
	mul.ftz.f32 	%f250, %f246, %f227;
	mul.ftz.f32 	%f249, %f245, %f227;
	mul.ftz.f32 	%f248, %f244, %f227;

BB1_62:
	.loc 1 43 1
	setp.eq.s32	%p65, %r4, 0;
	@%p65 bra 	BB1_64;

	mul.wide.s32 	%rd32, %r19, 16;
	add.s64 	%rd33, %rd1, %rd32;
	.loc 1 43 1
	st.global.v4.f32 	[%rd33], {%f248, %f249, %f250, %f251};
	bra.uni 	BB1_65;

BB1_64:
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f248;
	mov.b16 	%rs13, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f249;
	mov.b16 	%rs14, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f250;
	mov.b16 	%rs15, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f251;
	mov.b16 	%rs16, %temp;
}
	mul.wide.s32 	%rd35, %r19, 8;
	add.s64 	%rd36, %rd1, %rd35;
	.loc 1 43 241
	st.global.v4.u16 	[%rd36], {%rs13, %rs14, %rs15, %rs16};

BB1_65:
	.loc 1 43 2
	ret;
}


