//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Effects/Crop.cu", 1399785316, 2603
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry CropKernel(
	.param .u64 CropKernel_param_0,
	.param .u32 CropKernel_param_1,
	.param .u64 CropKernel_param_2,
	.param .u32 CropKernel_param_3,
	.param .u32 CropKernel_param_4,
	.param .u32 CropKernel_param_5,
	.param .u32 CropKernel_param_6,
	.param .u32 CropKernel_param_7,
	.param .u32 CropKernel_param_8,
	.param .u32 CropKernel_param_9,
	.param .u32 CropKernel_param_10,
	.param .u32 CropKernel_param_11,
	.param .u32 CropKernel_param_12,
	.param .f32 CropKernel_param_13,
	.param .f32 CropKernel_param_14
)
{
	.reg .pred 	%p<14>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<33>;
	.reg .f32 	%f<40>;
	.reg .s64 	%rd<13>;
	.reg .f64 	%fd<11>;


	ld.param.u64 	%rd3, [CropKernel_param_0];
	ld.param.u32 	%r7, [CropKernel_param_1];
	ld.param.u64 	%rd4, [CropKernel_param_2];
	ld.param.u32 	%r8, [CropKernel_param_3];
	ld.param.u32 	%r9, [CropKernel_param_4];
	ld.param.u32 	%r10, [CropKernel_param_5];
	ld.param.u32 	%r11, [CropKernel_param_6];
	ld.param.u32 	%r12, [CropKernel_param_7];
	ld.param.u32 	%r13, [CropKernel_param_8];
	ld.param.u32 	%r14, [CropKernel_param_9];
	ld.param.u32 	%r15, [CropKernel_param_10];
	ld.param.u32 	%r16, [CropKernel_param_11];
	ld.param.u32 	%r17, [CropKernel_param_12];
	ld.param.f32 	%f25, [CropKernel_param_13];
	ld.param.f32 	%f26, [CropKernel_param_14];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd3;
	.loc 1 28 1
	mov.u32 	%r18, %ntid.x;
	mov.u32 	%r19, %ctaid.x;
	mov.u32 	%r20, %tid.x;
	mad.lo.s32 	%r21, %r18, %r19, %r20;
	add.s32 	%r1, %r21, %r15;
	mov.u32 	%r22, %ntid.y;
	mov.u32 	%r23, %ctaid.y;
	mov.u32 	%r24, %tid.y;
	mad.lo.s32 	%r25, %r22, %r23, %r24;
	add.s32 	%r2, %r25, %r14;
	or.b32  	%r26, %r25, %r21;
	setp.gt.s32	%p1, %r26, -1;
	.loc 1 28 1
	setp.lt.s32	%p2, %r1, %r17;
	and.pred  	%p3, %p1, %p2;
	.loc 1 28 1
	setp.lt.s32	%p4, %r2, %r16;
	and.pred  	%p5, %p3, %p4;
	.loc 1 28 1
	@!%p5 bra 	BB0_11;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 28 1
	mad.lo.s32 	%r3, %r2, %r7, %r1;
	setp.eq.s32	%p6, %r9, 0;
	@%p6 bra 	BB0_3;

	mul.wide.s32 	%rd5, %r3, 16;
	add.s64 	%rd6, %rd2, %rd5;
	ld.global.v4.f32 	{%f27, %f28, %f29, %f30}, [%rd6];
	mov.f32 	%f38, %f30;
	mov.f32 	%f37, %f29;
	mov.f32 	%f36, %f28;
	mov.f32 	%f35, %f27;
	bra.uni 	BB0_4;

BB0_3:
	mul.wide.s32 	%rd7, %r3, 8;
	add.s64 	%rd8, %rd2, %rd7;
	.loc 1 28 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd8];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f35, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f36, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f37, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f38, %temp;
	}

BB0_4:
	.loc 1 28 1
	sub.s32 	%r27, %r1, %r13;
	setp.lt.s32	%p7, %r1, %r13;
	selp.b32	%r28, 0, %r27, %p7;
	sub.s32 	%r29, %r11, %r1;
	setp.lt.s32	%p8, %r1, %r11;
	selp.b32	%r4, %r29, %r28, %p8;
	sub.s32 	%r30, %r2, %r12;
	setp.lt.s32	%p9, %r2, %r12;
	selp.b32	%r31, 0, %r30, %p9;
	sub.s32 	%r32, %r10, %r2;
	setp.lt.s32	%p10, %r2, %r10;
	selp.b32	%r5, %r32, %r31, %p10;
	.loc 1 28 1
	setp.eq.s32	%p11, %r4, 0;
	mov.f32 	%f39, %f38;
	.loc 1 28 1
	@%p11 bra 	BB0_6;

	.loc 1 28 1
	cvt.rn.f32.s32	%f31, %r4;
	mul.ftz.f32 	%f32, %f31, %f25;
	cvt.ftz.f64.f32	%fd1, %f32;
	mov.f64 	%fd2, 0d3FF0000000000000;
	.loc 1 28 1
	sub.f64 	%fd3, %fd2, %fd1;
	cvt.ftz.f64.f32	%fd4, %f38;
	mul.f64 	%fd5, %fd4, %fd3;
	cvt.rn.ftz.f32.f64	%f39, %fd5;

BB0_6:
	.loc 1 28 1
	setp.eq.s32	%p12, %r5, 0;
	@%p12 bra 	BB0_8;

	.loc 1 28 1
	cvt.rn.f32.s32	%f33, %r5;
	mul.ftz.f32 	%f34, %f33, %f26;
	cvt.ftz.f64.f32	%fd6, %f34;
	mov.f64 	%fd7, 0d3FF0000000000000;
	.loc 1 28 1
	sub.f64 	%fd8, %fd7, %fd6;
	cvt.ftz.f64.f32	%fd9, %f39;
	mul.f64 	%fd10, %fd9, %fd8;
	cvt.rn.ftz.f32.f64	%f39, %fd10;

BB0_8:
	.loc 1 28 1
	mad.lo.s32 	%r6, %r2, %r8, %r1;
	.loc 1 28 1
	@%p6 bra 	BB0_10;

	mul.wide.s32 	%rd9, %r6, 16;
	add.s64 	%rd10, %rd1, %rd9;
	.loc 1 28 1
	st.global.v4.f32 	[%rd10], {%f35, %f36, %f37, %f39};
	bra.uni 	BB0_11;

BB0_10:
	mul.wide.s32 	%rd11, %r6, 8;
	add.s64 	%rd12, %rd1, %rd11;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f35;
	mov.b16 	%rs9, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f36;
	mov.b16 	%rs10, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f37;
	mov.b16 	%rs11, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f39;
	mov.b16 	%rs12, %temp;
}
	.loc 1 28 231
	st.global.v4.u16 	[%rd12], {%rs9, %rs10, %rs11, %rs12};

BB0_11:
	.loc 1 28 2
	ret;
}


