//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/GPUFoundation/Src/ImageProcessing/CopyAlpha.cu", 1399785310, 2706
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry CopyAlphaKernel(
	.param .u64 CopyAlphaKernel_param_0,
	.param .u32 CopyAlphaKernel_param_1,
	.param .u32 CopyAlphaKernel_param_2,
	.param .u32 CopyAlphaKernel_param_3,
	.param .u64 CopyAlphaKernel_param_4,
	.param .u32 CopyAlphaKernel_param_5,
	.param .u32 CopyAlphaKernel_param_6,
	.param .u32 CopyAlphaKernel_param_7,
	.param .u32 CopyAlphaKernel_param_8
)
{
	.reg .pred 	%p<8>;
	.reg .s16 	%rs<3>;
	.reg .s32 	%r<18>;
	.reg .f32 	%f<10>;
	.reg .s64 	%rd<11>;


	ld.param.u64 	%rd3, [CopyAlphaKernel_param_0];
	ld.param.u32 	%r4, [CopyAlphaKernel_param_1];
	ld.param.u32 	%r5, [CopyAlphaKernel_param_2];
	ld.param.u32 	%r6, [CopyAlphaKernel_param_3];
	ld.param.u64 	%rd4, [CopyAlphaKernel_param_4];
	ld.param.u32 	%r7, [CopyAlphaKernel_param_5];
	ld.param.u32 	%r8, [CopyAlphaKernel_param_6];
	ld.param.u32 	%r9, [CopyAlphaKernel_param_7];
	ld.param.u32 	%r10, [CopyAlphaKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd3;
	.loc 1 30 1
	mov.u32 	%r11, %ntid.x;
	mov.u32 	%r12, %ctaid.x;
	mov.u32 	%r13, %tid.x;
	mad.lo.s32 	%r1, %r11, %r12, %r13;
	mov.u32 	%r14, %ntid.y;
	mov.u32 	%r15, %ctaid.y;
	mov.u32 	%r16, %tid.y;
	mad.lo.s32 	%r2, %r14, %r15, %r16;
	.loc 1 30 1
	setp.lt.s32	%p1, %r1, %r9;
	setp.lt.s32	%p2, %r2, %r10;
	and.pred  	%p3, %p1, %p2;
	.loc 1 30 1
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 30 1
	setp.lt.s32	%p4, %r1, %r5;
	setp.lt.s32	%p5, %r2, %r6;
	and.pred  	%p6, %p4, %p5;
	.loc 1 30 1
	@%p6 bra 	BB0_3;

	mov.f32 	%f9, 0f00000000;
	bra.uni 	BB0_4;

BB0_3:
	.loc 1 30 1
	mad.lo.s32 	%r17, %r2, %r4, %r1;
	mul.wide.s32 	%rd5, %r17, 4;
	add.s64 	%rd6, %rd2, %rd5;
	.loc 1 30 1
	ld.global.f32 	%f9, [%rd6];

BB0_4:
	mov.f32 	%f5, 0f00000000;
	.loc 1 30 1
	mad.lo.s32 	%r3, %r2, %r7, %r1;
	.loc 1 30 1
	setp.eq.s32	%p7, %r8, 0;
	@%p7 bra 	BB0_6;

	mul.wide.s32 	%rd7, %r3, 16;
	add.s64 	%rd8, %rd1, %rd7;
	.loc 1 30 1
	st.global.v4.f32 	[%rd8], {%f5, %f5, %f5, %f9};
	bra.uni 	BB0_7;

BB0_6:
	mul.wide.s32 	%rd9, %r3, 8;
	add.s64 	%rd10, %rd1, %rd9;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs1, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f9;
	mov.b16 	%rs2, %temp;
}
	.loc 1 30 222
	st.global.v4.u16 	[%rd10], {%rs1, %rs1, %rs1, %rs2};

BB0_7:
	.loc 1 30 2
	ret;
}

.visible .entry CopyDeepAlphaKernel(
	.param .u64 CopyDeepAlphaKernel_param_0,
	.param .u32 CopyDeepAlphaKernel_param_1,
	.param .u32 CopyDeepAlphaKernel_param_2,
	.param .u32 CopyDeepAlphaKernel_param_3,
	.param .u64 CopyDeepAlphaKernel_param_4,
	.param .u32 CopyDeepAlphaKernel_param_5,
	.param .u32 CopyDeepAlphaKernel_param_6,
	.param .u32 CopyDeepAlphaKernel_param_7,
	.param .u32 CopyDeepAlphaKernel_param_8
)
{
	.reg .pred 	%p<9>;
	.reg .s16 	%rs<11>;
	.reg .s32 	%r<18>;
	.reg .f32 	%f<27>;
	.reg .s64 	%rd<13>;


	ld.param.u64 	%rd3, [CopyDeepAlphaKernel_param_0];
	ld.param.u32 	%r5, [CopyDeepAlphaKernel_param_1];
	ld.param.u32 	%r6, [CopyDeepAlphaKernel_param_2];
	ld.param.u32 	%r7, [CopyDeepAlphaKernel_param_3];
	ld.param.u64 	%rd4, [CopyDeepAlphaKernel_param_4];
	ld.param.u32 	%r8, [CopyDeepAlphaKernel_param_5];
	ld.param.u32 	%r9, [CopyDeepAlphaKernel_param_6];
	ld.param.u32 	%r10, [CopyDeepAlphaKernel_param_7];
	ld.param.u32 	%r11, [CopyDeepAlphaKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd3;
	.loc 1 30 1
	mov.u32 	%r12, %ntid.x;
	mov.u32 	%r13, %ctaid.x;
	mov.u32 	%r14, %tid.x;
	mad.lo.s32 	%r1, %r12, %r13, %r14;
	mov.u32 	%r15, %ntid.y;
	mov.u32 	%r16, %ctaid.y;
	mov.u32 	%r17, %tid.y;
	mad.lo.s32 	%r2, %r15, %r16, %r17;
	.loc 1 30 1
	setp.lt.s32	%p1, %r1, %r10;
	setp.lt.s32	%p2, %r2, %r11;
	and.pred  	%p3, %p1, %p2;
	.loc 1 30 1
	@!%p3 bra 	BB1_10;
	bra.uni 	BB1_1;

BB1_1:
	.loc 1 30 1
	setp.lt.s32	%p4, %r1, %r6;
	setp.lt.s32	%p5, %r2, %r7;
	and.pred  	%p6, %p4, %p5;
	.loc 1 30 1
	@%p6 bra 	BB1_3;

	mov.f32 	%f26, 0f00000000;
	bra.uni 	BB1_7;

BB1_3:
	setp.eq.s32	%p7, %r9, 0;
	.loc 1 30 1
	mad.lo.s32 	%r3, %r2, %r5, %r1;
	@%p7 bra 	BB1_5;

	mul.wide.s32 	%rd5, %r3, 16;
	add.s64 	%rd6, %rd2, %rd5;
	ld.global.v4.f32 	{%f20, %f21, %f22, %f23}, [%rd6];
	mov.f32 	%f25, %f23;
	mov.f32 	%f3, %f22;
	mov.f32 	%f2, %f21;
	mov.f32 	%f1, %f20;
	bra.uni 	BB1_6;

BB1_5:
	mul.wide.s32 	%rd7, %r3, 8;
	add.s64 	%rd8, %rd2, %rd7;
	.loc 1 30 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd8];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f25, %temp;
	}

BB1_6:
	mov.f32 	%f26, %f25;

BB1_7:
	mov.f32 	%f17, 0f00000000;
	.loc 1 30 1
	mad.lo.s32 	%r4, %r2, %r8, %r1;
	setp.eq.s32	%p8, %r9, 0;
	.loc 1 30 1
	@%p8 bra 	BB1_9;

	mul.wide.s32 	%rd9, %r4, 16;
	add.s64 	%rd10, %rd1, %rd9;
	.loc 1 30 1
	st.global.v4.f32 	[%rd10], {%f17, %f17, %f17, %f26};
	bra.uni 	BB1_10;

BB1_9:
	mul.wide.s32 	%rd11, %r4, 8;
	add.s64 	%rd12, %rd1, %rd11;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f17;
	mov.b16 	%rs9, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f26;
	mov.b16 	%rs10, %temp;
}
	.loc 1 30 231
	st.global.v4.u16 	[%rd12], {%rs9, %rs9, %rs9, %rs10};

BB1_10:
	.loc 1 30 2
	ret;
}


