//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/Iridas/IRIDASLIB/GPU/ASCCombined.cu", 1399785249, 2831
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\iridas\\iridaslib\\gpu\\IrGPGPUShaders.h", 1399785249, 44561
	.file	3 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .texref texture0_RECT;
// ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local has been demoted
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .func  (.param .b32 func_retval0) _Z5POWs_ff(
	.param .b32 _Z5POWs_ff_param_0,
	.param .b32 _Z5POWs_ff_param_1
)
{
	.reg .pred 	%p<5>;
	.reg .f32 	%f<10>;


	ld.param.f32 	%f3, [_Z5POWs_ff_param_0];
	ld.param.f32 	%f4, [_Z5POWs_ff_param_1];
	.loc 2 978 1
	setp.eq.ftz.f32	%p1, %f3, 0f00000000;
	setp.eq.ftz.f32	%p2, %f4, 0f00000000;
	and.pred  	%p3, %p1, %p2;
	.loc 2 978 1
	@!%p3 bra 	BB0_2;
	bra.uni 	BB0_1;

BB0_1:
	mov.f32 	%f9, 0f7FFFFFFF;
	bra.uni 	BB0_5;

BB0_2:
	.loc 2 978 1
	setp.geu.ftz.f32	%p4, %f4, 0f00000000;
	@%p4 bra 	BB0_4;

	mov.f32 	%f9, 0f3F800000;
	bra.uni 	BB0_5;

BB0_4:
	.loc 3 3600 10
	lg2.approx.ftz.f32 	%f5, %f3;
	mul.ftz.f32 	%f6, %f5, %f4;
	ex2.approx.ftz.f32 	%f9, %f6;

BB0_5:
	st.param.f32	[func_retval0+0], %f9;
	.loc 2 978 38
	ret;
}

.visible .entry ShaderKernel_ASCCombined(
	.param .u64 ShaderKernel_ASCCombined_param_0,
	.param .u32 ShaderKernel_ASCCombined_param_1,
	.param .u32 ShaderKernel_ASCCombined_param_2,
	.param .u32 ShaderKernel_ASCCombined_param_3,
	.param .u32 ShaderKernel_ASCCombined_param_4,
	.param .u64 ShaderKernel_ASCCombined_param_5,
	.param .u64 ShaderKernel_ASCCombined_param_6
)
{
	.reg .pred 	%p<21>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<93>;
	.reg .s64 	%rd<16>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local[64];

	ld.param.u64 	%rd3, [ShaderKernel_ASCCombined_param_0];
	ld.param.u32 	%r4, [ShaderKernel_ASCCombined_param_1];
	ld.param.u32 	%r5, [ShaderKernel_ASCCombined_param_2];
	ld.param.u32 	%r6, [ShaderKernel_ASCCombined_param_3];
	ld.param.u32 	%r7, [ShaderKernel_ASCCombined_param_4];
	ld.param.u64 	%rd4, [ShaderKernel_ASCCombined_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	.loc 1 31 1
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	.loc 1 31 1
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	.loc 1 31 1
	@!%p3 bra 	BB1_21;
	bra.uni 	BB1_1;

BB1_1:
	.loc 1 31 1
	cvt.rn.f32.s32	%f27, %r2;
	add.ftz.f32 	%f1, %f27, 0f3F000000;
	cvt.rn.f32.s32	%f28, %r3;
	add.ftz.f32 	%f2, %f28, 0f3F000000;
	.loc 1 31 1
	setp.gt.u32	%p4, %r1, 3;
	@%p4 bra 	BB1_3;

	.loc 1 31 1
	mul.wide.u32 	%rd5, %r1, 16;
	mov.u64 	%rd6, ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local;
	add.s64 	%rd7, %rd6, %rd5;
	add.s64 	%rd8, %rd1, %rd5;
	ld.global.v4.f32 	{%f29, %f30, %f31, %f32}, [%rd8];
	st.shared.v4.f32 	[%rd7], {%f29, %f30, %f31, %f32};

BB1_3:
	.loc 1 31 1
	bar.sync 	0;
	.loc 1 31 105
	// inline asm
	tex.2d.v4.f32.f32 {%f37, %f38, %f39, %f40}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	.loc 1 31 1
	ld.shared.v4.f32 	{%f43, %f44, %f45, %f46}, [ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local+16];
	ld.shared.v4.f32 	{%f48, %f49, %f50, %f51}, [ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local];
	.loc 1 31 1
	fma.rn.ftz.f32 	%f53, %f39, %f48, %f43;
	fma.rn.ftz.f32 	%f56, %f38, %f49, %f44;
	fma.rn.ftz.f32 	%f59, %f37, %f50, %f45;
	.loc 1 31 1
	setp.lt.ftz.f32	%p5, %f53, 0f00000000;
	selp.f32	%f4, 0fBF800000, 0f3F800000, %p5;
	setp.lt.ftz.f32	%p6, %f56, 0f00000000;
	selp.f32	%f5, 0fBF800000, 0f3F800000, %p6;
	setp.lt.ftz.f32	%p7, %f59, 0f00000000;
	selp.f32	%f6, 0fBF800000, 0f3F800000, %p7;
	.loc 3 2750 10
	abs.ftz.f32 	%f7, %f53;
	abs.ftz.f32 	%f8, %f56;
	abs.ftz.f32 	%f9, %f59;
	.loc 2 978 1
	setp.eq.ftz.f32	%p8, %f7, 0f00000000;
	.loc 1 31 1
	ld.shared.f32 	%f10, [ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local+32];
	.loc 2 978 1
	setp.eq.ftz.f32	%p9, %f10, 0f00000000;
	and.pred  	%p10, %p8, %p9;
	.loc 2 978 1
	@!%p10 bra 	BB1_5;
	bra.uni 	BB1_4;

BB1_4:
	mov.f32 	%f90, 0f7FFFFFFF;
	bra.uni 	BB1_8;

BB1_5:
	.loc 2 978 1
	setp.geu.ftz.f32	%p11, %f10, 0f00000000;
	@%p11 bra 	BB1_7;

	mov.f32 	%f90, 0f3F800000;
	bra.uni 	BB1_8;

BB1_7:
	.loc 3 3600 10
	lg2.approx.ftz.f32 	%f60, %f7;
	mul.ftz.f32 	%f61, %f10, %f60;
	ex2.approx.ftz.f32 	%f90, %f61;

BB1_8:
	.loc 1 31 1
	ld.shared.f32 	%f13, [ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local+36];
	.loc 2 978 1
	setp.eq.ftz.f32	%p12, %f13, 0f00000000;
	setp.eq.ftz.f32	%p13, %f8, 0f00000000;
	and.pred  	%p14, %p13, %p12;
	.loc 2 978 1
	@!%p14 bra 	BB1_10;
	bra.uni 	BB1_9;

BB1_9:
	mov.f32 	%f91, 0f7FFFFFFF;
	bra.uni 	BB1_13;

BB1_10:
	.loc 2 978 1
	setp.geu.ftz.f32	%p15, %f13, 0f00000000;
	@%p15 bra 	BB1_12;

	mov.f32 	%f91, 0f3F800000;
	bra.uni 	BB1_13;

BB1_12:
	.loc 3 3600 10
	lg2.approx.ftz.f32 	%f64, %f8;
	mul.ftz.f32 	%f65, %f13, %f64;
	ex2.approx.ftz.f32 	%f91, %f65;

BB1_13:
	.loc 1 31 1
	ld.shared.f32 	%f16, [ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local+40];
	.loc 2 978 1
	setp.eq.ftz.f32	%p16, %f16, 0f00000000;
	setp.eq.ftz.f32	%p17, %f9, 0f00000000;
	and.pred  	%p18, %p17, %p16;
	.loc 2 978 1
	@!%p18 bra 	BB1_15;
	bra.uni 	BB1_14;

BB1_14:
	mov.f32 	%f92, 0f7FFFFFFF;
	bra.uni 	BB1_18;

BB1_15:
	.loc 2 978 1
	setp.geu.ftz.f32	%p19, %f16, 0f00000000;
	@%p19 bra 	BB1_17;

	mov.f32 	%f92, 0f3F800000;
	bra.uni 	BB1_18;

BB1_17:
	.loc 3 3600 10
	lg2.approx.ftz.f32 	%f68, %f9;
	mul.ftz.f32 	%f69, %f16, %f68;
	ex2.approx.ftz.f32 	%f92, %f69;

BB1_18:
	.loc 1 31 1
	mul.ftz.f32 	%f72, %f90, %f4;
	mul.ftz.f32 	%f73, %f91, %f5;
	.loc 1 31 1
	mul.ftz.f32 	%f74, %f73, 0f3F371759;
	fma.rn.ftz.f32 	%f75, %f72, 0f3E59B3D0, %f74;
	.loc 1 31 1
	mul.ftz.f32 	%f76, %f92, %f6;
	.loc 1 31 1
	fma.rn.ftz.f32 	%f77, %f76, 0f3D93DD98, %f75;
	.loc 1 31 1
	sub.ftz.f32 	%f78, %f72, %f77;
	sub.ftz.f32 	%f79, %f73, %f77;
	sub.ftz.f32 	%f80, %f76, %f77;
	.loc 1 31 1
	ld.shared.v4.f32 	{%f81, %f82, %f83, %f84}, [ShaderKernel_ASCCombined$__cuda_local_var_170269_471_non_const_p_local+48];
	.loc 1 31 1
	fma.rn.ftz.f32 	%f19, %f78, %f81, %f77;
	fma.rn.ftz.f32 	%f20, %f79, %f82, %f77;
	fma.rn.ftz.f32 	%f21, %f80, %f83, %f77;
	.loc 1 31 1
	add.ftz.f32 	%f88, %f40, 0f80000000;
	.loc 1 31 1
	fma.rn.ftz.f32 	%f22, %f88, %f84, 0f00000000;
	.loc 1 31 1
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	.loc 1 31 1
	cvt.s64.s32	%rd2, %r13;
	.loc 1 31 1
	setp.eq.s32	%p20, %r5, 0;
	@%p20 bra 	BB1_20;

	cvta.to.global.u64 	%rd10, %rd3;
	.loc 1 31 1
	shl.b64 	%rd11, %rd2, 4;
	add.s64 	%rd12, %rd10, %rd11;
	st.global.v4.f32 	[%rd12], {%f21, %f20, %f19, %f22};
	bra.uni 	BB1_21;

BB1_20:
	cvta.to.global.u64 	%rd13, %rd3;
	.loc 1 31 1
	shl.b64 	%rd14, %rd2, 3;
	add.s64 	%rd15, %rd13, %rd14;
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f21;
	mov.b16 	%rs1, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs2, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs3, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs4, %temp;
}
	.loc 1 31 231
	st.global.v4.u16 	[%rd15], {%rs1, %rs2, %rs3, %rs4};

BB1_21:
	.loc 1 31 2
	ret;
}


