//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/GPUFoundation/Src/ImageProcessing/AlphaGain.cu", 1399785310, 2840
	.file	2 "D:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\MediaCore\\GPUFoundation\\API\\Inc\\GPUFoundation/KernelSupport/PixelUtils.h", 1399785310, 5707
	.file	3 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .func  (.param .align 16 .b8 func_retval0[16]) _Z18UnpremultiplyPixel8PixelRGB(
	.param .align 16 .b8 _Z18UnpremultiplyPixel8PixelRGB_param_0[16]
)
{
	.reg .pred 	%p<2>;
	.reg .f32 	%f<24>;


	ld.param.f32 	%f3, [_Z18UnpremultiplyPixel8PixelRGB_param_0+8];
	ld.param.f32 	%f2, [_Z18UnpremultiplyPixel8PixelRGB_param_0+4];
	ld.param.f32 	%f1, [_Z18UnpremultiplyPixel8PixelRGB_param_0];
	ld.param.f32 	%f12, [_Z18UnpremultiplyPixel8PixelRGB_param_0+12];
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f20, %f12;
	.loc 2 45 1
	add.ftz.f32 	%f13, %f20, 0fB70637BD;
	setp.gtu.ftz.f32	%p1, %f13, 0f00000000;
	@%p1 bra 	BB0_2;

	mov.f32 	%f23, 0f00000000;
	mov.f32 	%f22, %f23;
	mov.f32 	%f21, %f23;
	mov.f32 	%f20, %f23;
	bra.uni 	BB0_3;

BB0_2:
	mov.f32 	%f18, 0f3F800000;
	.loc 3 3606 10
	div.approx.ftz.f32 	%f19, %f18, %f20;
	.loc 2 45 1
	mul.ftz.f32 	%f21, %f3, %f19;
	mul.ftz.f32 	%f22, %f2, %f19;
	mul.ftz.f32 	%f23, %f1, %f19;

BB0_3:
	st.param.f32	[func_retval0+0], %f23;
	st.param.f32	[func_retval0+4], %f22;
	st.param.f32	[func_retval0+8], %f21;
	st.param.f32	[func_retval0+12], %f20;
	.loc 2 45 1
	ret;
}

.visible .entry AlphaGainKernel(
	.param .u64 AlphaGainKernel_param_0,
	.param .u32 AlphaGainKernel_param_1,
	.param .u64 AlphaGainKernel_param_2,
	.param .u32 AlphaGainKernel_param_3,
	.param .u32 AlphaGainKernel_param_4,
	.param .u32 AlphaGainKernel_param_5,
	.param .u32 AlphaGainKernel_param_6,
	.param .f32 AlphaGainKernel_param_7
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<16>;
	.reg .f32 	%f<30>;
	.reg .s64 	%rd<13>;


	ld.param.u64 	%rd3, [AlphaGainKernel_param_0];
	ld.param.u32 	%r5, [AlphaGainKernel_param_1];
	ld.param.u64 	%rd4, [AlphaGainKernel_param_2];
	ld.param.u32 	%r6, [AlphaGainKernel_param_3];
	ld.param.u32 	%r7, [AlphaGainKernel_param_4];
	ld.param.u32 	%r8, [AlphaGainKernel_param_5];
	ld.param.u32 	%r9, [AlphaGainKernel_param_6];
	ld.param.f32 	%f21, [AlphaGainKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd3;
	.loc 1 30 1
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r10, %r11, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r13, %r14, %r15;
	.loc 1 30 1
	setp.lt.s32	%p1, %r1, %r8;
	setp.lt.s32	%p2, %r2, %r9;
	and.pred  	%p3, %p1, %p2;
	.loc 1 30 1
	@!%p3 bra 	BB1_7;
	bra.uni 	BB1_1;

BB1_1:
	.loc 1 30 1
	mad.lo.s32 	%r3, %r2, %r5, %r1;
	setp.eq.s32	%p4, %r7, 0;
	@%p4 bra 	BB1_3;

	mul.wide.s32 	%rd5, %r3, 16;
	add.s64 	%rd6, %rd2, %rd5;
	ld.global.v4.f32 	{%f22, %f23, %f24, %f25}, [%rd6];
	mov.f32 	%f29, %f25;
	mov.f32 	%f28, %f24;
	mov.f32 	%f27, %f23;
	mov.f32 	%f26, %f22;
	bra.uni 	BB1_4;

BB1_3:
	mul.wide.s32 	%rd7, %r3, 8;
	add.s64 	%rd8, %rd2, %rd7;
	.loc 1 30 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd8];
	.loc 3 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f26, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f27, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f28, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f29, %temp;
	}

BB1_4:
	.loc 1 30 1
	mul.ftz.f32 	%f20, %f29, %f21;
	.loc 1 30 1
	mad.lo.s32 	%r4, %r2, %r6, %r1;
	.loc 1 30 1
	@%p4 bra 	BB1_6;

	mul.wide.s32 	%rd9, %r4, 16;
	add.s64 	%rd10, %rd1, %rd9;
	.loc 1 30 1
	st.global.v4.f32 	[%rd10], {%f26, %f27, %f28, %f20};
	bra.uni 	BB1_7;

BB1_6:
	mul.wide.s32 	%rd11, %r4, 8;
	add.s64 	%rd12, %rd1, %rd11;
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f26;
	mov.b16 	%rs9, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f27;
	mov.b16 	%rs10, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f28;
	mov.b16 	%rs11, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs12, %temp;
}
	.loc 1 30 231
	st.global.v4.u16 	[%rd12], {%rs9, %rs10, %rs11, %rs12};

BB1_7:
	.loc 1 30 2
	ret;
}

.visible .entry UnpremultiplyKernel(
	.param .u64 UnpremultiplyKernel_param_0,
	.param .u32 UnpremultiplyKernel_param_1,
	.param .u64 UnpremultiplyKernel_param_2,
	.param .u32 UnpremultiplyKernel_param_3,
	.param .u32 UnpremultiplyKernel_param_4,
	.param .u32 UnpremultiplyKernel_param_5,
	.param .u32 UnpremultiplyKernel_param_6,
	.param .align 16 .b8 UnpremultiplyKernel_param_7[16]
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<16>;
	.reg .f32 	%f<59>;
	.reg .s64 	%rd<13>;


	ld.param.u64 	%rd3, [UnpremultiplyKernel_param_0];
	ld.param.u32 	%r5, [UnpremultiplyKernel_param_1];
	ld.param.u64 	%rd4, [UnpremultiplyKernel_param_2];
	ld.param.u32 	%r6, [UnpremultiplyKernel_param_3];
	ld.param.u32 	%r7, [UnpremultiplyKernel_param_4];
	ld.param.u32 	%r8, [UnpremultiplyKernel_param_5];
	ld.param.u32 	%r9, [UnpremultiplyKernel_param_6];
	ld.param.f32 	%f30, [UnpremultiplyKernel_param_7+8];
	ld.param.f32 	%f29, [UnpremultiplyKernel_param_7+4];
	ld.param.f32 	%f28, [UnpremultiplyKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd4;
	cvta.to.global.u64 	%rd2, %rd3;
	.loc 1 30 1
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r10, %r11, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r13, %r14, %r15;
	.loc 1 30 1
	setp.lt.s32	%p1, %r1, %r8;
	setp.lt.s32	%p2, %r2, %r9;
	and.pred  	%p3, %p1, %p2;
	.loc 1 30 1
	@!%p3 bra 	BB2_10;
	bra.uni 	BB2_1;

BB2_1:
	.loc 1 30 1
	mad.lo.s32 	%r3, %r2, %r5, %r1;
	setp.eq.s32	%p4, %r7, 0;
	@%p4 bra 	BB2_3;

	mul.wide.s32 	%rd5, %r3, 16;
	add.s64 	%rd6, %rd2, %rd5;
	ld.global.v4.f32 	{%f32, %f33, %f34, %f35}, [%rd6];
	mov.f32 	%f54, %f35;
	mov.f32 	%f53, %f34;
	mov.f32 	%f52, %f33;
	mov.f32 	%f51, %f32;
	bra.uni 	BB2_4;

BB2_3:
	mul.wide.s32 	%rd7, %r3, 8;
	add.s64 	%rd8, %rd2, %rd7;
	.loc 1 30 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd8];
	.loc 3 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f51, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f52, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f53, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f54, %temp;
	}

BB2_4:
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f55, %f54;
	mov.f32 	%f36, 0f3F800000;
	.loc 1 30 124
	sub.ftz.f32 	%f37, %f36, %f55;
	.loc 1 30 1
	mul.ftz.f32 	%f38, %f30, %f37;
	mul.ftz.f32 	%f39, %f29, %f37;
	mul.ftz.f32 	%f40, %f28, %f37;
	sub.ftz.f32 	%f41, %f51, %f40;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f14, %f41;
	.loc 1 30 1
	sub.ftz.f32 	%f42, %f52, %f39;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f15, %f42;
	.loc 1 30 1
	sub.ftz.f32 	%f43, %f53, %f38;
	.loc 3 2820 10
	cvt.ftz.sat.f32.f32	%f16, %f43;
	.loc 2 45 1
	add.ftz.f32 	%f44, %f55, 0fB70637BD;
	setp.gtu.ftz.f32	%p5, %f44, 0f00000000;
	@%p5 bra 	BB2_6;

	mov.f32 	%f58, 0f00000000;
	mov.f32 	%f57, %f58;
	mov.f32 	%f56, %f58;
	mov.f32 	%f55, %f58;
	bra.uni 	BB2_7;

BB2_6:
	.loc 3 3606 10
	div.approx.ftz.f32 	%f50, %f36, %f55;
	.loc 2 45 1
	mul.ftz.f32 	%f56, %f16, %f50;
	mul.ftz.f32 	%f57, %f15, %f50;
	mul.ftz.f32 	%f58, %f14, %f50;

BB2_7:
	.loc 1 30 1
	mad.lo.s32 	%r4, %r2, %r6, %r1;
	.loc 1 30 1
	@%p4 bra 	BB2_9;

	mul.wide.s32 	%rd9, %r4, 16;
	add.s64 	%rd10, %rd1, %rd9;
	.loc 1 30 1
	st.global.v4.f32 	[%rd10], {%f58, %f57, %f56, %f55};
	bra.uni 	BB2_10;

BB2_9:
	mul.wide.s32 	%rd11, %r4, 8;
	add.s64 	%rd12, %rd1, %rd11;
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f58;
	mov.b16 	%rs9, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f57;
	mov.b16 	%rs10, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f56;
	mov.b16 	%rs11, %temp;
}
	.loc 3 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f55;
	mov.b16 	%rs12, %temp;
}
	.loc 1 30 231
	st.global.v4.u16 	[%rd12], {%rs9, %rs10, %rs11, %rs12};

BB2_10:
	.loc 1 30 2
	ret;
}


