//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Wed Jul 10 12:41:20 2013 (1373485280)
// Cuda compilation tools, release 5.5, V5.5.0
//

.version 3.2
.target sm_30
.address_size 64

	.file	1 "D:/singlebarrel/releases/2014.03/shared/adobe/MediaCore/Renderers/RendererGPU/Src/Effects/AdditiveDissolve.cu", 1399785316, 2721
	.file	2 "d:\\singlebarrel\\releases\\2014.03\\shared\\adobe\\mediacore\\external\\3rdparty\\nvidia\\cuda\\win\\include\\device_functions.h", 1399785281, 191626
.global .align 1 .b8 $str[11] = {95, 95, 67, 85, 68, 65, 95, 70, 84, 90, 0};

.visible .entry AdditiveDissolveKernel(
	.param .u64 AdditiveDissolveKernel_param_0,
	.param .u32 AdditiveDissolveKernel_param_1,
	.param .u64 AdditiveDissolveKernel_param_2,
	.param .u32 AdditiveDissolveKernel_param_3,
	.param .u64 AdditiveDissolveKernel_param_4,
	.param .u32 AdditiveDissolveKernel_param_5,
	.param .u32 AdditiveDissolveKernel_param_6,
	.param .u32 AdditiveDissolveKernel_param_7,
	.param .u32 AdditiveDissolveKernel_param_8,
	.param .f32 AdditiveDissolveKernel_param_9
)
{
	.reg .pred 	%p<8>;
	.reg .s16 	%rs<21>;
	.reg .s32 	%r<18>;
	.reg .f32 	%f<84>;
	.reg .s64 	%rd<19>;


	ld.param.u64 	%rd4, [AdditiveDissolveKernel_param_0];
	ld.param.u32 	%r6, [AdditiveDissolveKernel_param_1];
	ld.param.u64 	%rd5, [AdditiveDissolveKernel_param_2];
	ld.param.u32 	%r7, [AdditiveDissolveKernel_param_3];
	ld.param.u64 	%rd6, [AdditiveDissolveKernel_param_4];
	ld.param.u32 	%r8, [AdditiveDissolveKernel_param_5];
	ld.param.u32 	%r9, [AdditiveDissolveKernel_param_6];
	ld.param.u32 	%r10, [AdditiveDissolveKernel_param_7];
	ld.param.u32 	%r11, [AdditiveDissolveKernel_param_8];
	ld.param.f32 	%f48, [AdditiveDissolveKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	cvta.to.global.u64 	%rd3, %rd4;
	.loc 1 27 1
	mov.u32 	%r12, %ntid.x;
	mov.u32 	%r13, %ctaid.x;
	mov.u32 	%r14, %tid.x;
	mad.lo.s32 	%r1, %r12, %r13, %r14;
	mov.u32 	%r15, %ntid.y;
	mov.u32 	%r16, %ctaid.y;
	mov.u32 	%r17, %tid.y;
	mad.lo.s32 	%r2, %r15, %r16, %r17;
	.loc 1 27 1
	setp.lt.s32	%p1, %r1, %r10;
	setp.lt.s32	%p2, %r2, %r11;
	and.pred  	%p3, %p1, %p2;
	.loc 1 27 1
	@!%p3 bra 	BB0_13;
	bra.uni 	BB0_1;

BB0_1:
	.loc 1 27 1
	mad.lo.s32 	%r3, %r2, %r6, %r1;
	setp.eq.s32	%p4, %r9, 0;
	@%p4 bra 	BB0_3;

	mul.wide.s32 	%rd7, %r3, 16;
	add.s64 	%rd8, %rd3, %rd7;
	ld.global.v4.f32 	{%f49, %f50, %f51, %f52}, [%rd8];
	mov.f32 	%f75, %f52;
	mov.f32 	%f74, %f51;
	mov.f32 	%f73, %f50;
	mov.f32 	%f72, %f49;
	bra.uni 	BB0_4;

BB0_3:
	mul.wide.s32 	%rd9, %r3, 8;
	add.s64 	%rd10, %rd3, %rd9;
	.loc 1 27 1
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f72, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f73, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f74, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f75, %temp;
	}

BB0_4:
	.loc 1 27 1
	mad.lo.s32 	%r4, %r2, %r7, %r1;
	@%p4 bra 	BB0_6;

	mul.wide.s32 	%rd11, %r4, 16;
	add.s64 	%rd12, %rd2, %rd11;
	ld.global.v4.f32 	{%f53, %f54, %f55, %f56}, [%rd12];
	mov.f32 	%f79, %f56;
	mov.f32 	%f78, %f55;
	mov.f32 	%f77, %f54;
	mov.f32 	%f76, %f53;
	bra.uni 	BB0_7;

BB0_6:
	mul.wide.s32 	%rd13, %r4, 8;
	add.s64 	%rd14, %rd2, %rd13;
	.loc 1 27 1
	ld.global.v4.u16 	{%rs9, %rs10, %rs11, %rs12}, [%rd14];
	.loc 2 3518 10
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs9;
	cvt.f32.f16 	%f76, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs10;
	cvt.f32.f16 	%f77, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs11;
	cvt.f32.f16 	%f78, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs12;
	cvt.f32.f16 	%f79, %temp;
	}

BB0_7:
	.loc 1 27 1
	mul.ftz.f32 	%f31, %f75, %f79;
	.loc 1 27 1
	setp.gtu.ftz.f32	%p6, %f48, 0f3F800000;
	@%p6 bra 	BB0_9;

	.loc 1 27 1
	fma.rn.ftz.f32 	%f57, %f76, %f48, %f72;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f80, %f57;
	.loc 1 27 1
	fma.rn.ftz.f32 	%f58, %f77, %f48, %f73;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f81, %f58;
	.loc 1 27 1
	fma.rn.ftz.f32 	%f59, %f78, %f48, %f74;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f82, %f59;
	mov.f32 	%f60, 0f3F800000;
	.loc 1 27 1
	sub.ftz.f32 	%f61, %f60, %f48;
	mul.ftz.f32 	%f62, %f31, %f48;
	fma.rn.ftz.f32 	%f63, %f75, %f61, %f62;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f83, %f63;
	bra.uni 	BB0_10;

BB0_9:
	mov.f32 	%f64, 0f40000000;
	.loc 1 27 1
	sub.ftz.f32 	%f65, %f64, %f48;
	fma.rn.ftz.f32 	%f66, %f72, %f65, %f76;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f80, %f66;
	.loc 1 27 1
	fma.rn.ftz.f32 	%f67, %f73, %f65, %f77;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f81, %f67;
	.loc 1 27 1
	fma.rn.ftz.f32 	%f68, %f74, %f65, %f78;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f82, %f68;
	.loc 1 27 1
	add.ftz.f32 	%f69, %f48, 0fBF800000;
	mul.ftz.f32 	%f70, %f79, %f69;
	fma.rn.ftz.f32 	%f71, %f31, %f65, %f70;
	.loc 2 2820 10
	cvt.ftz.sat.f32.f32	%f83, %f71;

BB0_10:
	.loc 1 27 1
	mad.lo.s32 	%r5, %r2, %r8, %r1;
	.loc 1 27 1
	@%p4 bra 	BB0_12;

	mul.wide.s32 	%rd15, %r5, 16;
	add.s64 	%rd16, %rd1, %rd15;
	.loc 1 27 1
	st.global.v4.f32 	[%rd16], {%f80, %f81, %f82, %f83};
	bra.uni 	BB0_13;

BB0_12:
	mul.wide.s32 	%rd17, %r5, 8;
	add.s64 	%rd18, %rd1, %rd17;
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f80;
	mov.b16 	%rs17, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f81;
	mov.b16 	%rs18, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f82;
	mov.b16 	%rs19, %temp;
}
	.loc 2 3513 10
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f83;
	mov.b16 	%rs20, %temp;
}
	.loc 1 27 231
	st.global.v4.u16 	[%rd18], {%rs17, %rs18, %rs19, %rs20};

BB0_13:
	.loc 1 27 2
	ret;
}


