//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .func  (.param .b32 func_retval0) _Z5clampIfET_S0_S0_S0_(
	.param .b32 _Z5clampIfET_S0_S0_S0__param_0,
	.param .b32 _Z5clampIfET_S0_S0_S0__param_1,
	.param .b32 _Z5clampIfET_S0_S0_S0__param_2
)
{
	.reg .f32 	%f<6>;


	ld.param.f32 	%f1, [_Z5clampIfET_S0_S0_S0__param_0];
	ld.param.f32 	%f2, [_Z5clampIfET_S0_S0_S0__param_1];
	ld.param.f32 	%f3, [_Z5clampIfET_S0_S0_S0__param_2];
	max.ftz.f32 	%f4, %f1, %f2;
	min.ftz.f32 	%f5, %f4, %f3;
	st.param.f32	[func_retval0+0], %f5;
	ret;
}

.visible .entry WipeKernel(
	.param .u64 WipeKernel_param_0,
	.param .u32 WipeKernel_param_1,
	.param .u64 WipeKernel_param_2,
	.param .u32 WipeKernel_param_3,
	.param .u64 WipeKernel_param_4,
	.param .u32 WipeKernel_param_5,
	.param .u32 WipeKernel_param_6,
	.param .u32 WipeKernel_param_7,
	.param .u32 WipeKernel_param_8,
	.param .u32 WipeKernel_param_9,
	.param .u32 WipeKernel_param_10,
	.param .u32 WipeKernel_param_11,
	.param .u32 WipeKernel_param_12,
	.param .f32 WipeKernel_param_13,
	.param .f32 WipeKernel_param_14,
	.param .f32 WipeKernel_param_15,
	.param .f32 WipeKernel_param_16,
	.param .f32 WipeKernel_param_17,
	.param .f32 WipeKernel_param_18,
	.param .f32 WipeKernel_param_19
)
{
	.reg .pred 	%p<16>;
	.reg .s16 	%rs<37>;
	.reg .s32 	%r<28>;
	.reg .f32 	%f<140>;
	.reg .s64 	%rd<20>;


	ld.param.u64 	%rd7, [WipeKernel_param_0];
	ld.param.u32 	%r7, [WipeKernel_param_1];
	ld.param.u64 	%rd8, [WipeKernel_param_2];
	ld.param.u32 	%r8, [WipeKernel_param_3];
	ld.param.u64 	%rd9, [WipeKernel_param_4];
	ld.param.u32 	%r9, [WipeKernel_param_5];
	ld.param.u32 	%r10, [WipeKernel_param_6];
	ld.param.u32 	%r11, [WipeKernel_param_7];
	ld.param.u32 	%r12, [WipeKernel_param_8];
	ld.param.u32 	%r15, [WipeKernel_param_9];
	ld.param.u32 	%r13, [WipeKernel_param_10];
	ld.param.u32 	%r16, [WipeKernel_param_11];
	ld.param.u32 	%r14, [WipeKernel_param_12];
	ld.param.f32 	%f75, [WipeKernel_param_13];
	ld.param.f32 	%f76, [WipeKernel_param_14];
	ld.param.f32 	%f77, [WipeKernel_param_15];
	ld.param.f32 	%f78, [WipeKernel_param_16];
	ld.param.f32 	%f79, [WipeKernel_param_17];
	ld.param.f32 	%f80, [WipeKernel_param_18];
	ld.param.f32 	%f81, [WipeKernel_param_19];
	cvta.to.global.u64 	%rd1, %rd9;
	mov.u32 	%r17, %ntid.x;
	mov.u32 	%r18, %ctaid.x;
	mov.u32 	%r19, %tid.x;
	mad.lo.s32 	%r1, %r17, %r18, %r19;
	add.s32 	%r2, %r1, %r15;
	mov.u32 	%r20, %ntid.y;
	mov.u32 	%r21, %ctaid.y;
	mov.u32 	%r22, %tid.y;
	mad.lo.s32 	%r3, %r20, %r21, %r22;
	add.s32 	%r4, %r3, %r13;
	setp.gt.s32	%p1, %r1, -1;
	add.s32 	%r23, %r16, %r15;
	setp.lt.s32	%p2, %r2, %r23;
	and.pred  	%p3, %p1, %p2;
	setp.gt.s32	%p4, %r3, -1;
	and.pred  	%p5, %p3, %p4;
	@!%p5 bra 	BB1_22;
	bra.uni 	BB1_1;

BB1_1:
	add.s32 	%r24, %r14, %r13;
	setp.ge.s32	%p6, %r4, %r24;
	@%p6 bra 	BB1_22;

	cvta.to.global.u64 	%rd10, %rd8;
	add.s32 	%r5, %r1, %r11;
	cvt.rn.f32.s32	%f82, %r2;
	cvt.rn.f32.s32	%f83, %r4;
	mul.ftz.f32 	%f84, %f83, %f81;
	fma.rn.ftz.f32 	%f85, %f82, %f80, %f84;
	add.ftz.f32 	%f1, %f85, %f78;
	add.ftz.f32 	%f2, %f85, %f79;
	setp.ltu.ftz.f32	%p7, %f2, 0f3F800000;
	add.s32 	%r6, %r3, %r12;
	mad.lo.s32 	%r25, %r6, %r8, %r5;
	mul.wide.s32 	%rd11, %r25, 16;
	add.s64 	%rd2, %rd10, %rd11;
	mul.wide.s32 	%rd12, %r25, 8;
	add.s64 	%rd3, %rd10, %rd12;
	@%p7 bra 	BB1_7;

	setp.eq.s32	%p8, %r10, 0;
	@%p8 bra 	BB1_5;

	ld.global.v4.f32 	{%f86, %f87, %f88, %f89}, [%rd2];
	mov.f32 	%f123, %f89;
	mov.f32 	%f122, %f88;
	mov.f32 	%f121, %f87;
	mov.f32 	%f120, %f86;
	bra.uni 	BB1_6;

BB1_5:
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd3];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f120, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f121, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f122, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f123, %temp;
	}

BB1_6:
	mov.f32 	%f136, %f120;
	mov.f32 	%f137, %f121;
	mov.f32 	%f138, %f122;
	mov.f32 	%f139, %f123;
	bra.uni 	BB1_19;

BB1_7:
	cvta.to.global.u64 	%rd13, %rd7;
	setp.le.ftz.f32	%p9, %f1, 0f00000000;
	setp.le.ftz.f32	%p10, %f2, 0f00000000;
	and.pred  	%p11, %p10, %p9;
	mad.lo.s32 	%r26, %r6, %r7, %r5;
	mul.wide.s32 	%rd14, %r26, 16;
	add.s64 	%rd4, %rd13, %rd14;
	mul.wide.s32 	%rd15, %r26, 8;
	add.s64 	%rd5, %rd13, %rd15;
	@%p11 bra 	BB1_15;

	setp.eq.s32	%p12, %r10, 0;
	@%p12 bra 	BB1_10;

	ld.global.v4.f32 	{%f90, %f91, %f92, %f93}, [%rd4];
	mov.f32 	%f127, %f93;
	mov.f32 	%f126, %f92;
	mov.f32 	%f125, %f91;
	mov.f32 	%f124, %f90;
	bra.uni 	BB1_11;

BB1_10:
	ld.global.v4.u16 	{%rs9, %rs10, %rs11, %rs12}, [%rd5];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs9;
	cvt.f32.f16 	%f124, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs10;
	cvt.f32.f16 	%f125, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs11;
	cvt.f32.f16 	%f126, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs12;
	cvt.f32.f16 	%f127, %temp;
	}

BB1_11:
	@%p12 bra 	BB1_13;

	ld.global.v4.f32 	{%f94, %f95, %f96, %f97}, [%rd2];
	mov.f32 	%f131, %f97;
	mov.f32 	%f130, %f96;
	mov.f32 	%f129, %f95;
	mov.f32 	%f128, %f94;
	bra.uni 	BB1_14;

BB1_13:
	ld.global.v4.u16 	{%rs17, %rs18, %rs19, %rs20}, [%rd3];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs17;
	cvt.f32.f16 	%f128, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs18;
	cvt.f32.f16 	%f129, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs19;
	cvt.f32.f16 	%f130, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs20;
	cvt.f32.f16 	%f131, %temp;
	}

BB1_14:
	mov.f32 	%f98, 0f00000000;
	max.ftz.f32 	%f99, %f1, %f98;
	mov.f32 	%f100, 0f3F800000;
	min.ftz.f32 	%f101, %f99, %f100;
	sub.ftz.f32 	%f102, %f75, %f124;
	fma.rn.ftz.f32 	%f103, %f101, %f102, %f124;
	sub.ftz.f32 	%f104, %f76, %f125;
	fma.rn.ftz.f32 	%f105, %f101, %f104, %f125;
	sub.ftz.f32 	%f106, %f77, %f126;
	fma.rn.ftz.f32 	%f107, %f101, %f106, %f126;
	sub.ftz.f32 	%f108, %f100, %f127;
	fma.rn.ftz.f32 	%f109, %f101, %f108, %f127;
	max.ftz.f32 	%f110, %f2, %f98;
	min.ftz.f32 	%f111, %f110, %f100;
	sub.ftz.f32 	%f112, %f128, %f103;
	fma.rn.ftz.f32 	%f136, %f111, %f112, %f103;
	sub.ftz.f32 	%f113, %f129, %f105;
	fma.rn.ftz.f32 	%f137, %f111, %f113, %f105;
	sub.ftz.f32 	%f114, %f130, %f107;
	fma.rn.ftz.f32 	%f138, %f111, %f114, %f107;
	sub.ftz.f32 	%f115, %f131, %f109;
	fma.rn.ftz.f32 	%f139, %f111, %f115, %f109;
	bra.uni 	BB1_19;

BB1_15:
	setp.eq.s32	%p14, %r10, 0;
	@%p14 bra 	BB1_17;

	ld.global.v4.f32 	{%f116, %f117, %f118, %f119}, [%rd4];
	mov.f32 	%f135, %f119;
	mov.f32 	%f134, %f118;
	mov.f32 	%f133, %f117;
	mov.f32 	%f132, %f116;
	bra.uni 	BB1_18;

BB1_17:
	ld.global.v4.u16 	{%rs25, %rs26, %rs27, %rs28}, [%rd5];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs25;
	cvt.f32.f16 	%f132, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs26;
	cvt.f32.f16 	%f133, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs27;
	cvt.f32.f16 	%f134, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs28;
	cvt.f32.f16 	%f135, %temp;
	}

BB1_18:
	mov.f32 	%f136, %f132;
	mov.f32 	%f137, %f133;
	mov.f32 	%f138, %f134;
	mov.f32 	%f139, %f135;

BB1_19:
	mad.lo.s32 	%r27, %r4, %r9, %r2;
	cvt.s64.s32	%rd6, %r27;
	setp.eq.s32	%p15, %r10, 0;
	@%p15 bra 	BB1_21;

	shl.b64 	%rd16, %rd6, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f136, %f137, %f138, %f139};
	bra.uni 	BB1_22;

BB1_21:
	shl.b64 	%rd18, %rd6, 3;
	add.s64 	%rd19, %rd1, %rd18;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f139;
	mov.b16 	%rs33, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f138;
	mov.b16 	%rs34, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f137;
	mov.b16 	%rs35, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f136;
	mov.b16 	%rs36, %temp;
}
	st.global.v4.u16 	[%rd19], {%rs36, %rs35, %rs34, %rs33};

BB1_22:
	ret;
}


