//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.const .align 4 .b8 kRGB32f_To_601YPbPr[36] = {135, 22, 153, 62, 162, 69, 22, 63, 213, 120, 233, 61, 33, 201, 44, 190, 111, 155, 169, 190, 0, 0, 0, 63, 0, 0, 0, 63, 70, 94, 214, 190, 232, 134, 166, 189};
.const .align 4 .b8 k601YPbPr_To_RGB32f[36] = {0, 0, 128, 63, 0, 0, 0, 0, 188, 116, 179, 63, 0, 0, 128, 63, 152, 50, 176, 190, 158, 209, 54, 191, 0, 0, 128, 63, 229, 208, 226, 63, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_601YCbCr[36] = {70, 246, 130, 66, 145, 141, 0, 67, 94, 186, 199, 65, 33, 48, 23, 194, 240, 103, 148, 194, 0, 0, 224, 66, 0, 0, 224, 66, 111, 146, 187, 194, 70, 182, 145, 193};
.const .align 4 .b8 k601YCbCr_To_RGB32f[36] = {37, 160, 149, 59, 0, 0, 0, 0, 182, 23, 205, 59, 37, 160, 149, 59, 40, 15, 201, 186, 156, 239, 80, 187, 37, 160, 149, 59, 236, 155, 1, 60, 0, 0, 0, 0};
.const .align 4 .b8 kRGB8u_To_601YCbCr[36] = {219, 121, 131, 62, 152, 14, 1, 63, 18, 131, 200, 61, 174, 199, 23, 190, 238, 252, 148, 190, 197, 224, 224, 62, 197, 224, 224, 62, 217, 78, 188, 190, 174, 71, 146, 189};
.const .align 4 .b8 k601YCbCr_To_RGB8u[36] = {127, 10, 149, 63, 0, 0, 0, 0, 160, 74, 204, 63, 127, 10, 149, 63, 254, 148, 200, 190, 184, 30, 80, 191, 127, 10, 149, 63, 78, 26, 1, 64, 0, 0, 0, 0};
.const .align 4 .b8 kRGB8u_To_601YCbCrFullRange[36] = {135, 22, 153, 62, 162, 69, 22, 63, 213, 120, 233, 61, 166, 27, 44, 190, 39, 241, 168, 190, 250, 254, 254, 62, 250, 254, 254, 62, 43, 135, 213, 190, 59, 223, 165, 189};
.const .align 4 .b8 k601YCbCrFullRange_To_RGB8u[36] = {0, 0, 128, 63, 0, 0, 0, 0, 72, 193, 178, 63, 0, 0, 128, 63, 143, 130, 175, 190, 225, 26, 54, 191, 0, 0, 128, 63, 20, 238, 225, 63, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_601YCbCrFullRange[36] = {113, 125, 152, 66, 92, 175, 21, 67, 92, 143, 232, 65, 158, 111, 43, 194, 49, 72, 168, 194, 0, 0, 254, 66, 0, 0, 254, 66, 170, 177, 212, 194, 88, 57, 165, 193};
.const .align 4 .b8 k601YCbCrFullRange_To_RGB32f[36] = {129, 128, 128, 59, 0, 0, 0, 0, 188, 116, 179, 59, 129, 128, 128, 59, 194, 50, 176, 186, 179, 209, 54, 187, 129, 128, 128, 59, 229, 208, 226, 59, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_709YPbPr[36] = {208, 179, 89, 62, 89, 23, 55, 63, 152, 221, 147, 61, 186, 164, 234, 189, 210, 86, 197, 190, 0, 0, 0, 63, 0, 0, 0, 63, 190, 134, 232, 190, 16, 202, 59, 189};
.const .align 4 .b8 k709YPbPr_To_RGB32f[36] = {0, 0, 128, 63, 0, 0, 0, 0, 12, 147, 201, 63, 0, 0, 128, 63, 221, 209, 63, 190, 243, 173, 239, 190, 0, 0, 128, 63, 77, 132, 237, 63, 0, 0, 0, 0};
.const .align 4 .b8 kRGB32f_To_709YCbCr[36] = {106, 60, 58, 66, 6, 161, 28, 67, 244, 253, 124, 65, 223, 79, 205, 193, 8, 172, 172, 194, 0, 0, 224, 66, 0, 0, 224, 66, 195, 117, 203, 194, 236, 81, 36, 193};
.const .align 4 .b8 k709YCbCr_To_RGB32f[36] = {37, 160, 149, 59, 0, 0, 0, 0, 239, 94, 230, 59, 37, 160, 149, 59, 33, 57, 91, 186, 178, 245, 8, 187, 37, 160, 149, 59, 82, 185, 7, 60, 0, 0, 0, 0};
.const .align 4 .b8 k709YCbCrFullRange_To_RGB32f[36] = {131, 128, 128, 59, 0, 0, 0, 0, 28, 147, 201, 59, 131, 128, 128, 59, 61, 210, 63, 186, 248, 173, 239, 186, 131, 128, 128, 59, 82, 132, 237, 59, 0, 0, 0, 0};
.const .align 4 .b8 kRGB8u_To_709YCbCr[36] = {207, 247, 58, 62, 53, 62, 29, 63, 231, 251, 125, 61, 184, 30, 206, 189, 23, 89, 173, 190, 197, 224, 224, 62, 197, 224, 224, 62, 12, 66, 204, 190, 195, 245, 36, 189};
.const .align 4 .b8 k709YCbCr_To_RGB8u[36] = {127, 10, 149, 63, 0, 0, 0, 0, 147, 120, 229, 63, 127, 10, 149, 63, 53, 94, 90, 190, 205, 108, 8, 191, 127, 10, 149, 63, 154, 49, 7, 64, 0, 0, 0, 0};
.const .align 4 .b8 k709YCbCr_To_601YCbCr[36] = {0, 0, 128, 63, 23, 100, 203, 61, 1, 77, 68, 62, 0, 0, 0, 0, 18, 103, 125, 63, 10, 158, 226, 189, 0, 0, 0, 0, 61, 98, 148, 189, 249, 191, 123, 63};
.const .align 4 .b8 k601YCbCr_To_709YCbCr[36] = {0, 0, 128, 63, 122, 165, 236, 189, 179, 237, 84, 190, 0, 0, 0, 0, 204, 98, 130, 63, 216, 188, 234, 61, 0, 0, 0, 0, 74, 179, 153, 61, 234, 61, 131, 63};
.const .align 4 .b8 kYCbCrOffset[12] = {0, 0, 128, 65, 0, 0, 0, 67, 0, 0, 0, 67};
.const .align 4 .b8 kYCbCrFullRangeOffset[12] = {0, 0, 0, 0, 0, 0, 0, 67, 0, 0, 0, 67};

.visible .entry TrackMatteKernel(
	.param .u64 TrackMatteKernel_param_0,
	.param .u32 TrackMatteKernel_param_1,
	.param .u32 TrackMatteKernel_param_2,
	.param .u32 TrackMatteKernel_param_3,
	.param .u64 TrackMatteKernel_param_4,
	.param .u32 TrackMatteKernel_param_5,
	.param .u32 TrackMatteKernel_param_6,
	.param .u32 TrackMatteKernel_param_7,
	.param .u32 TrackMatteKernel_param_8,
	.param .u32 TrackMatteKernel_param_9,
	.param .u32 TrackMatteKernel_param_10
)
{
	.reg .pred 	%p<19>;
	.reg .s16 	%rs<22>;
	.reg .s32 	%r<24>;
	.reg .f32 	%f<105>;
	.reg .s64 	%rd<15>;


	ld.param.u64 	%rd4, [TrackMatteKernel_param_0];
	ld.param.u32 	%r5, [TrackMatteKernel_param_1];
	ld.param.u32 	%r12, [TrackMatteKernel_param_2];
	ld.param.u32 	%r13, [TrackMatteKernel_param_3];
	ld.param.u64 	%rd5, [TrackMatteKernel_param_4];
	ld.param.u32 	%r6, [TrackMatteKernel_param_5];
	ld.param.u32 	%r7, [TrackMatteKernel_param_6];
	ld.param.u32 	%r8, [TrackMatteKernel_param_7];
	ld.param.u32 	%r9, [TrackMatteKernel_param_8];
	ld.param.u32 	%r10, [TrackMatteKernel_param_9];
	ld.param.u32 	%r11, [TrackMatteKernel_param_10];
	mov.u32 	%r14, %ntid.x;
	mov.u32 	%r15, %ctaid.x;
	mov.u32 	%r16, %tid.x;
	mad.lo.s32 	%r1, %r14, %r15, %r16;
	mov.u32 	%r17, %ntid.y;
	mov.u32 	%r18, %ctaid.y;
	mov.u32 	%r19, %tid.y;
	mad.lo.s32 	%r2, %r17, %r18, %r19;
	cvt.rn.f32.s32	%f41, %r1;
	sub.s32 	%r20, %r12, %r7;
	cvt.rn.f32.s32	%f42, %r20;
	mul.ftz.f32 	%f43, %f42, 0f3F000000;
	sub.ftz.f32 	%f44, %f41, %f43;
	add.ftz.f32 	%f45, %f44, 0f3F000000;
	cvt.rzi.ftz.s32.f32	%r3, %f45;
	cvt.rn.f32.s32	%f46, %r2;
	sub.s32 	%r21, %r13, %r8;
	cvt.rn.f32.s32	%f47, %r21;
	mul.ftz.f32 	%f48, %f47, 0f3F000000;
	sub.ftz.f32 	%f49, %f46, %f48;
	add.ftz.f32 	%f50, %f49, 0f3F000000;
	cvt.rzi.ftz.s32.f32	%r4, %f50;
	setp.lt.s32	%p1, %r1, %r12;
	setp.lt.s32	%p2, %r2, %r13;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_18;
	bra.uni 	BB0_1;

BB0_1:
	cvta.to.global.u64 	%rd6, %rd4;
	setp.gt.s32	%p4, %r3, -1;
	setp.lt.s32	%p5, %r3, %r7;
	and.pred  	%p6, %p4, %p5;
	setp.gt.s32	%p7, %r4, -1;
	and.pred  	%p8, %p6, %p7;
	setp.lt.s32	%p9, %r4, %r8;
	and.pred  	%p10, %p8, %p9;
	mad.lo.s32 	%r22, %r2, %r5, %r1;
	mul.wide.s32 	%rd7, %r22, 16;
	add.s64 	%rd1, %rd6, %rd7;
	mul.wide.s32 	%rd8, %r22, 8;
	add.s64 	%rd2, %rd6, %rd8;
	@%p10 bra 	BB0_6;

	setp.ne.s32	%p11, %r11, 0;
	@%p11 bra 	BB0_18;

	setp.eq.s32	%p12, %r9, 0;
	@%p12 bra 	BB0_5;

	mov.f32 	%f51, 0f00000000;
	st.global.v4.f32 	[%rd1], {%f51, %f51, %f51, %f51};
	bra.uni 	BB0_18;

BB0_5:
	mov.f32 	%f52, 0f00000000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f52;
	mov.b16 	%rs1, %temp;
}
	st.global.v4.u16 	[%rd2], {%rs1, %rs1, %rs1, %rs1};
	bra.uni 	BB0_18;

BB0_6:
	setp.eq.s32	%p13, %r9, 0;
	@%p13 bra 	BB0_8;

	ld.global.v4.f32 	{%f53, %f54, %f55, %f56}, [%rd1];
	mov.f32 	%f99, %f56;
	mov.f32 	%f98, %f55;
	mov.f32 	%f97, %f54;
	mov.f32 	%f96, %f53;
	bra.uni 	BB0_9;

BB0_8:
	ld.global.v4.u16 	{%rs2, %rs3, %rs4, %rs5}, [%rd2];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f96, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f97, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f98, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs5;
	cvt.f32.f16 	%f99, %temp;
	}

BB0_9:
	ld.const.f32 	%f14, [kRGB32f_To_601YPbPr];
	ld.const.f32 	%f15, [kRGB32f_To_601YPbPr+4];
	mul.ftz.f32 	%f57, %f97, %f15;
	fma.rn.ftz.f32 	%f58, %f98, %f14, %f57;
	ld.const.f32 	%f16, [kRGB32f_To_601YPbPr+8];
	fma.rn.ftz.f32 	%f17, %f96, %f16, %f58;
	ld.const.f32 	%f59, [kRGB32f_To_601YPbPr+12];
	ld.const.f32 	%f60, [kRGB32f_To_601YPbPr+16];
	mul.ftz.f32 	%f61, %f97, %f60;
	fma.rn.ftz.f32 	%f62, %f98, %f59, %f61;
	ld.const.f32 	%f63, [kRGB32f_To_601YPbPr+20];
	fma.rn.ftz.f32 	%f18, %f96, %f63, %f62;
	ld.const.f32 	%f64, [kRGB32f_To_601YPbPr+24];
	ld.const.f32 	%f65, [kRGB32f_To_601YPbPr+28];
	mul.ftz.f32 	%f66, %f97, %f65;
	fma.rn.ftz.f32 	%f67, %f98, %f64, %f66;
	ld.const.f32 	%f68, [kRGB32f_To_601YPbPr+32];
	fma.rn.ftz.f32 	%f19, %f96, %f68, %f67;
	mad.lo.s32 	%r23, %r4, %r6, %r3;
	cvt.s64.s32	%rd3, %r23;
	@%p13 bra 	BB0_11;

	cvta.to.global.u64 	%rd9, %rd5;
	shl.b64 	%rd10, %rd3, 4;
	add.s64 	%rd11, %rd9, %rd10;
	ld.global.v4.f32 	{%f69, %f70, %f71, %f72}, [%rd11];
	mov.f32 	%f103, %f72;
	mov.f32 	%f102, %f71;
	mov.f32 	%f101, %f70;
	mov.f32 	%f100, %f69;
	bra.uni 	BB0_12;

BB0_11:
	cvta.to.global.u64 	%rd12, %rd5;
	shl.b64 	%rd13, %rd3, 3;
	add.s64 	%rd14, %rd12, %rd13;
	ld.global.v4.u16 	{%rs10, %rs11, %rs12, %rs13}, [%rd14];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs10;
	cvt.f32.f16 	%f100, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs11;
	cvt.f32.f16 	%f101, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs12;
	cvt.f32.f16 	%f102, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs13;
	cvt.f32.f16 	%f103, %temp;
	}

BB0_12:
	mul.ftz.f32 	%f73, %f101, %f15;
	fma.rn.ftz.f32 	%f74, %f102, %f14, %f73;
	fma.rn.ftz.f32 	%f33, %f100, %f16, %f74;
	setp.eq.s32	%p15, %r10, 0;
	@%p15 bra 	BB0_14;

	setp.eq.s32	%p16, %r11, 0;
	cvt.ftz.sat.f32.f32	%f75, %f33;
	mul.ftz.f32 	%f76, %f103, %f75;
	mov.f32 	%f77, 0f3F800000;
	sub.ftz.f32 	%f78, %f77, %f76;
	selp.f32	%f104, %f76, %f78, %p16;
	bra.uni 	BB0_15;

BB0_14:
	setp.eq.s32	%p17, %r11, 0;
	mov.f32 	%f79, 0f3F800000;
	sub.ftz.f32 	%f80, %f79, %f103;
	selp.f32	%f104, %f103, %f80, %p17;

BB0_15:
	ld.const.f32 	%f81, [k601YPbPr_To_RGB32f];
	ld.const.f32 	%f82, [k601YPbPr_To_RGB32f+4];
	mul.ftz.f32 	%f83, %f18, %f82;
	fma.rn.ftz.f32 	%f84, %f17, %f81, %f83;
	ld.const.f32 	%f85, [k601YPbPr_To_RGB32f+8];
	fma.rn.ftz.f32 	%f37, %f19, %f85, %f84;
	ld.const.f32 	%f86, [k601YPbPr_To_RGB32f+12];
	ld.const.f32 	%f87, [k601YPbPr_To_RGB32f+16];
	mul.ftz.f32 	%f88, %f18, %f87;
	fma.rn.ftz.f32 	%f89, %f17, %f86, %f88;
	ld.const.f32 	%f90, [k601YPbPr_To_RGB32f+20];
	fma.rn.ftz.f32 	%f38, %f19, %f90, %f89;
	ld.const.f32 	%f91, [k601YPbPr_To_RGB32f+24];
	ld.const.f32 	%f92, [k601YPbPr_To_RGB32f+28];
	mul.ftz.f32 	%f93, %f18, %f92;
	fma.rn.ftz.f32 	%f94, %f17, %f91, %f93;
	ld.const.f32 	%f95, [k601YPbPr_To_RGB32f+32];
	fma.rn.ftz.f32 	%f39, %f19, %f95, %f94;
	mul.ftz.f32 	%f40, %f99, %f104;
	@%p13 bra 	BB0_17;

	st.global.v4.f32 	[%rd1], {%f39, %f38, %f37, %f40};
	bra.uni 	BB0_18;

BB0_17:
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f40;
	mov.b16 	%rs18, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f37;
	mov.b16 	%rs19, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f38;
	mov.b16 	%rs20, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f39;
	mov.b16 	%rs21, %temp;
}
	st.global.v4.u16 	[%rd2], {%rs21, %rs20, %rs19, %rs18};

BB0_18:
	ret;
}


