//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry cuda_kernel_timecode(
	.param .u64 cuda_kernel_timecode_param_0,
	.param .u32 cuda_kernel_timecode_param_1,
	.param .u32 cuda_kernel_timecode_param_2,
	.param .u64 cuda_kernel_timecode_param_3,
	.param .u32 cuda_kernel_timecode_param_4,
	.param .u32 cuda_kernel_timecode_param_5,
	.param .u32 cuda_kernel_timecode_param_6,
	.param .u32 cuda_kernel_timecode_param_7,
	.param .u32 cuda_kernel_timecode_param_8,
	.param .u32 cuda_kernel_timecode_param_9,
	.param .f32 cuda_kernel_timecode_param_10,
	.param .u32 cuda_kernel_timecode_param_11
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<15>;
	.reg .s32 	%r<24>;
	.reg .f32 	%f<43>;
	.reg .s64 	%rd<11>;


	ld.param.u64 	%rd3, [cuda_kernel_timecode_param_0];
	ld.param.u32 	%r3, [cuda_kernel_timecode_param_1];
	ld.param.u32 	%r4, [cuda_kernel_timecode_param_2];
	ld.param.u64 	%rd4, [cuda_kernel_timecode_param_3];
	ld.param.u32 	%r10, [cuda_kernel_timecode_param_4];
	ld.param.u32 	%r11, [cuda_kernel_timecode_param_5];
	ld.param.u32 	%r5, [cuda_kernel_timecode_param_6];
	ld.param.u32 	%r6, [cuda_kernel_timecode_param_7];
	ld.param.u32 	%r7, [cuda_kernel_timecode_param_8];
	ld.param.u32 	%r8, [cuda_kernel_timecode_param_9];
	ld.param.f32 	%f21, [cuda_kernel_timecode_param_10];
	ld.param.u32 	%r9, [cuda_kernel_timecode_param_11];
	mov.u32 	%r12, %ntid.x;
	mov.u32 	%r13, %ctaid.x;
	mov.u32 	%r14, %tid.x;
	mad.lo.s32 	%r1, %r12, %r13, %r14;
	mov.u32 	%r15, %ntid.y;
	mov.u32 	%r16, %ctaid.y;
	mov.u32 	%r17, %tid.y;
	mad.lo.s32 	%r2, %r15, %r16, %r17;
	setp.ge.s32	%p1, %r2, %r11;
	setp.ge.s32	%p2, %r1, %r10;
	or.pred  	%p3, %p2, %p1;
	@%p3 bra 	BB0_10;

	cvta.to.global.u64 	%rd5, %rd4;
	cvta.to.global.u64 	%rd6, %rd3;
	add.s32 	%r18, %r2, %r4;
	add.s32 	%r19, %r1, %r3;
	mad.lo.s32 	%r20, %r18, %r7, %r19;
	mul.wide.s32 	%rd7, %r20, 4;
	add.s64 	%rd8, %rd6, %rd7;
	ld.global.u8 	%rs1, [%rd8];
	add.s32 	%r21, %r2, %r6;
	add.s32 	%r22, %r1, %r5;
	mad.lo.s32 	%r23, %r21, %r8, %r22;
	mul.wide.s32 	%rd9, %r23, 16;
	add.s64 	%rd1, %rd5, %rd9;
	mul.wide.s32 	%rd10, %r23, 8;
	add.s64 	%rd2, %rd5, %rd10;
	setp.eq.s32	%p4, %r9, 0;
	@%p4 bra 	BB0_3;

	ld.global.v4.f32 	{%f22, %f23, %f24, %f25}, [%rd1];
	mov.f32 	%f41, %f25;
	mov.f32 	%f40, %f24;
	mov.f32 	%f39, %f23;
	mov.f32 	%f38, %f22;
	bra.uni 	BB0_4;

BB0_3:
	ld.global.v4.u16 	{%rs2, %rs3, %rs4, %rs5}, [%rd2];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f38, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f39, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f40, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs5;
	cvt.f32.f16 	%f41, %temp;
	}

BB0_4:
	and.b16  	%rs10, %rs1, 255;
	cvt.rn.f32.u16	%f26, %rs10;
	mov.f32 	%f27, 0f437F0000;
	div.approx.ftz.f32 	%f13, %f26, %f27;
	mov.f32 	%f28, 0f3F800000;
	sub.ftz.f32 	%f29, %f28, %f13;
	fma.rn.ftz.f32 	%f30, %f29, %f21, %f13;
	cvt.ftz.sat.f32.f32	%f31, %f41;
	sub.ftz.f32 	%f32, %f28, %f30;
	mul.ftz.f32 	%f14, %f31, %f32;
	add.ftz.f32 	%f15, %f30, %f14;
	setp.neu.ftz.f32	%p5, %f15, 0f00000000;
	@%p5 bra 	BB0_6;

	mov.f32 	%f42, 0f00000000;
	bra.uni 	BB0_7;

BB0_6:
	div.approx.ftz.f32 	%f42, %f28, %f15;

BB0_7:
	fma.rn.ftz.f32 	%f35, %f38, %f14, %f13;
	mul.ftz.f32 	%f18, %f35, %f42;
	fma.rn.ftz.f32 	%f36, %f39, %f14, %f13;
	mul.ftz.f32 	%f19, %f36, %f42;
	fma.rn.ftz.f32 	%f37, %f40, %f14, %f13;
	mul.ftz.f32 	%f20, %f37, %f42;
	@%p4 bra 	BB0_9;

	st.global.v4.f32 	[%rd1], {%f18, %f19, %f20, %f15};
	bra.uni 	BB0_10;

BB0_9:
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f15;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs12, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs13, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f18;
	mov.b16 	%rs14, %temp;
}
	st.global.v4.u16 	[%rd2], {%rs14, %rs13, %rs12, %rs11};

BB0_10:
	ret;
}


