//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref inSrcTexture;

.visible .entry SharpenKernel(
	.param .u64 SharpenKernel_param_0,
	.param .u64 SharpenKernel_param_1,
	.param .u32 SharpenKernel_param_2,
	.param .u32 SharpenKernel_param_3,
	.param .u32 SharpenKernel_param_4,
	.param .u32 SharpenKernel_param_5,
	.param .f32 SharpenKernel_param_6,
	.param .f32 SharpenKernel_param_7
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<55>;
	.reg .s64 	%rd<18>;


	ld.param.u64 	%rd3, [SharpenKernel_param_1];
	ld.param.u32 	%r3, [SharpenKernel_param_2];
	ld.param.u32 	%r4, [SharpenKernel_param_3];
	ld.param.u32 	%r5, [SharpenKernel_param_4];
	ld.param.u32 	%r6, [SharpenKernel_param_5];
	ld.param.f32 	%f5, [SharpenKernel_param_6];
	ld.param.f32 	%f6, [SharpenKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f37, %r1;
	add.ftz.f32 	%f35, %f37, 0f3F000000;
	cvt.rn.f32.s32	%f38, %r2;
	add.ftz.f32 	%f12, %f38, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f7, %f8, %f9, %f10}, [inSrcTexture, {%f35, %f12}];
	// inline asm
	add.ftz.f32 	%f17, %f37, 0fBF000000;
	add.ftz.f32 	%f30, %f38, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f13, %f14, %f15, %f16}, [inSrcTexture, {%f17, %f30}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f19, %f20, %f21, %f22}, [inSrcTexture, {%f35, %f30}];
	// inline asm
	add.ftz.f32 	%f29, %f37, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f25, %f26, %f27, %f28}, [inSrcTexture, {%f29, %f30}];
	// inline asm
	add.ftz.f32 	%f36, %f38, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f31, %f32, %f33, %f34}, [inSrcTexture, {%f35, %f36}];
	// inline asm
	add.ftz.f32 	%f39, %f7, %f13;
	add.ftz.f32 	%f40, %f8, %f14;
	add.ftz.f32 	%f41, %f9, %f15;
	add.ftz.f32 	%f42, %f10, %f16;
	add.ftz.f32 	%f43, %f39, %f25;
	add.ftz.f32 	%f44, %f40, %f26;
	add.ftz.f32 	%f45, %f41, %f27;
	add.ftz.f32 	%f46, %f42, %f28;
	add.ftz.f32 	%f47, %f43, %f31;
	add.ftz.f32 	%f48, %f44, %f32;
	add.ftz.f32 	%f49, %f45, %f33;
	add.ftz.f32 	%f50, %f46, %f34;
	mul.ftz.f32 	%f51, %f47, %f6;
	mul.ftz.f32 	%f52, %f48, %f6;
	mul.ftz.f32 	%f53, %f49, %f6;
	mul.ftz.f32 	%f54, %f50, %f6;
	fma.rn.ftz.f32 	%f1, %f19, %f5, %f51;
	fma.rn.ftz.f32 	%f2, %f20, %f5, %f52;
	fma.rn.ftz.f32 	%f3, %f21, %f5, %f53;
	fma.rn.ftz.f32 	%f4, %f22, %f5, %f54;
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p4, %r4, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd14, %rd2, 4;
	add.s64 	%rd15, %rd1, %rd14;
	st.global.v4.f32 	[%rd15], {%f1, %f2, %f3, %f4};
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd16, %rd2, 3;
	add.s64 	%rd17, %rd1, %rd16;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f2;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f1;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd17], {%rs4, %rs3, %rs2, %rs1};

BB0_4:
	ret;
}


