//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
.global .texref texture1_RECT;
// ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local has been demoted

.visible .entry ShaderKernel_SecondaryPass4(
	.param .u64 ShaderKernel_SecondaryPass4_param_0,
	.param .u32 ShaderKernel_SecondaryPass4_param_1,
	.param .u32 ShaderKernel_SecondaryPass4_param_2,
	.param .u32 ShaderKernel_SecondaryPass4_param_3,
	.param .u32 ShaderKernel_SecondaryPass4_param_4,
	.param .u64 ShaderKernel_SecondaryPass4_param_5,
	.param .u64 ShaderKernel_SecondaryPass4_param_6,
	.param .u64 ShaderKernel_SecondaryPass4_param_7
)
{
	.reg .pred 	%p<12>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<22>;
	.reg .f32 	%f<216>;
	.reg .s64 	%rd<35>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local[160];

	ld.param.u64 	%rd2, [ShaderKernel_SecondaryPass4_param_0];
	ld.param.u32 	%r4, [ShaderKernel_SecondaryPass4_param_1];
	ld.param.u32 	%r5, [ShaderKernel_SecondaryPass4_param_2];
	ld.param.u32 	%r6, [ShaderKernel_SecondaryPass4_param_3];
	ld.param.u32 	%r7, [ShaderKernel_SecondaryPass4_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_SecondaryPass4_param_5];
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_15;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 9;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd4, %rd3;
	mul.wide.u32 	%rd5, %r1, 16;
	mov.u64 	%rd6, ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local;
	add.s64 	%rd7, %rd6, %rd5;
	add.s64 	%rd8, %rd4, %rd5;
	ld.global.v4.f32 	{%f32, %f33, %f34, %f35}, [%rd8];
	st.shared.v4.f32 	[%rd7], {%f32, %f33, %f34, %f35};

BB0_3:
	cvt.rn.f32.s32	%f40, %r2;
	add.ftz.f32 	%f1, %f40, 0f3F000000;
	cvt.rn.f32.s32	%f41, %r3;
	add.ftz.f32 	%f2, %f41, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f42, %f43, %f44, %f45}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	add.ftz.f32 	%f94, %f1, 0f00000000;
	add.ftz.f32 	%f53, %f2, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f48, %f49, %f50, %f51}, [texture0_RECT, {%f94, %f53}];
	// inline asm
	add.ftz.f32 	%f59, %f2, 0fC0000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f54, %f55, %f56, %f57}, [texture0_RECT, {%f94, %f59}];
	// inline asm
	add.ftz.f32 	%f65, %f2, 0fC0400000;
	// inline asm
	tex.2d.v4.f32.f32 {%f60, %f61, %f62, %f63}, [texture0_RECT, {%f94, %f65}];
	// inline asm
	add.ftz.f32 	%f71, %f2, 0fC0800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f66, %f67, %f68, %f69}, [texture0_RECT, {%f94, %f71}];
	// inline asm
	ld.shared.v4.f32 	{%f102, %f103, %f104, %f105}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+48];
	mul.ftz.f32 	%f107, %f51, %f102;
	mul.ftz.f32 	%f109, %f57, %f103;
	mul.ftz.f32 	%f111, %f63, %f104;
	mul.ftz.f32 	%f113, %f69, %f105;
	add.ftz.f32 	%f77, %f2, 0f3F800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f72, %f73, %f74, %f75}, [texture0_RECT, {%f94, %f77}];
	// inline asm
	add.ftz.f32 	%f83, %f2, 0f40000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f78, %f79, %f80, %f81}, [texture0_RECT, {%f94, %f83}];
	// inline asm
	add.ftz.f32 	%f89, %f2, 0f40400000;
	// inline asm
	tex.2d.v4.f32.f32 {%f84, %f85, %f86, %f87}, [texture0_RECT, {%f94, %f89}];
	// inline asm
	add.ftz.f32 	%f95, %f2, 0f40800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f90, %f91, %f92, %f93}, [texture0_RECT, {%f94, %f95}];
	// inline asm
	fma.rn.ftz.f32 	%f114, %f75, %f102, %f107;
	fma.rn.ftz.f32 	%f115, %f81, %f103, %f109;
	fma.rn.ftz.f32 	%f116, %f87, %f104, %f111;
	fma.rn.ftz.f32 	%f117, %f93, %f105, %f113;
	add.ftz.f32 	%f118, %f114, %f115;
	add.ftz.f32 	%f119, %f118, %f116;
	add.ftz.f32 	%f120, %f119, %f117;
	add.ftz.f32 	%f7, %f120, %f45;
	// inline asm
	tex.2d.v4.f32.f32 {%f96, %f97, %f98, %f99}, [texture1_RECT, {%f1, %f2}];
	// inline asm
	ld.shared.v4.f32 	{%f121, %f122, %f123, %f124}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+112];
	mul.ftz.f32 	%f125, %f43, %f122;
	fma.rn.ftz.f32 	%f126, %f44, %f121, %f125;
	fma.rn.ftz.f32 	%f127, %f42, %f123, %f126;
	sub.ftz.f32 	%f128, %f44, %f127;
	sub.ftz.f32 	%f129, %f43, %f127;
	sub.ftz.f32 	%f130, %f42, %f127;
	ld.shared.v4.f32 	{%f131, %f132, %f133, %f134}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+128];
	fma.rn.ftz.f32 	%f136, %f128, %f131, %f127;
	fma.rn.ftz.f32 	%f138, %f129, %f132, %f127;
	fma.rn.ftz.f32 	%f140, %f130, %f133, %f127;
	ld.shared.v4.f32 	{%f141, %f142, %f143, %f144}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+32];
	ld.shared.v4.f32 	{%f145, %f146, %f147, %f148}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local];
	fma.rn.ftz.f32 	%f16, %f136, %f141, %f145;
	fma.rn.ftz.f32 	%f17, %f138, %f142, %f146;
	fma.rn.ftz.f32 	%f18, %f140, %f143, %f147;
	abs.ftz.f32 	%f19, %f16;
	abs.ftz.f32 	%f20, %f17;
	abs.ftz.f32 	%f21, %f18;
	setp.gtu.ftz.f32	%p5, %f19, 0f00000000;
	@%p5 bra 	BB0_5;

	mov.f32 	%f213, 0f00000000;
	bra.uni 	BB0_6;

BB0_5:
	ld.shared.f32 	%f156, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+16];
	lg2.approx.ftz.f32 	%f157, %f19;
	mul.ftz.f32 	%f158, %f157, %f156;
	ex2.approx.ftz.f32 	%f213, %f158;

BB0_6:
	setp.gtu.ftz.f32	%p6, %f20, 0f00000000;
	@%p6 bra 	BB0_8;

	mov.f32 	%f214, 0f00000000;
	bra.uni 	BB0_9;

BB0_8:
	ld.shared.f32 	%f160, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+20];
	lg2.approx.ftz.f32 	%f161, %f20;
	mul.ftz.f32 	%f162, %f161, %f160;
	ex2.approx.ftz.f32 	%f214, %f162;

BB0_9:
	setp.gtu.ftz.f32	%p7, %f21, 0f00000000;
	@%p7 bra 	BB0_11;

	mov.f32 	%f215, 0f00000000;
	bra.uni 	BB0_12;

BB0_11:
	ld.shared.f32 	%f164, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+24];
	lg2.approx.ftz.f32 	%f165, %f21;
	mul.ftz.f32 	%f166, %f165, %f164;
	ex2.approx.ftz.f32 	%f215, %f166;

BB0_12:
	ld.shared.f32 	%f167, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+76];
	mul.ftz.f32 	%f168, %f7, %f167;
	setp.lt.ftz.f32	%p8, %f16, 0f00000000;
	selp.f32	%f169, 0fBF800000, 0f3F800000, %p8;
	mov.f32 	%f170, 0f3F800000;
	setp.lt.ftz.f32	%p9, %f17, 0f00000000;
	selp.f32	%f171, 0fBF800000, 0f3F800000, %p9;
	setp.lt.ftz.f32	%p10, %f18, 0f00000000;
	selp.f32	%f172, 0fBF800000, 0f3F800000, %p10;
	mul.ftz.f32 	%f173, %f213, %f169;
	mul.ftz.f32 	%f174, %f214, %f171;
	mul.ftz.f32 	%f175, %f174, %f122;
	fma.rn.ftz.f32 	%f176, %f173, %f121, %f175;
	mul.ftz.f32 	%f177, %f215, %f172;
	fma.rn.ftz.f32 	%f178, %f177, %f123, %f176;
	sub.ftz.f32 	%f179, %f173, %f178;
	sub.ftz.f32 	%f180, %f174, %f178;
	sub.ftz.f32 	%f181, %f177, %f178;
	ld.shared.v4.f32 	{%f182, %f183, %f184, %f185}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+144];
	fma.rn.ftz.f32 	%f187, %f179, %f182, %f178;
	fma.rn.ftz.f32 	%f189, %f180, %f183, %f178;
	fma.rn.ftz.f32 	%f191, %f181, %f184, %f178;
	ld.shared.v4.f32 	{%f192, %f193, %f194, %f195}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+80];
	ld.shared.v4.f32 	{%f196, %f197, %f198, %f199}, [ShaderKernel_SecondaryPass4$__cuda_local_var_180682_639_non_const_p_local+96];
	fma.rn.ftz.f32 	%f202, %f44, %f192, %f196;
	fma.rn.ftz.f32 	%f205, %f43, %f193, %f197;
	fma.rn.ftz.f32 	%f208, %f42, %f194, %f198;
	sub.ftz.f32 	%f209, %f170, %f168;
	mul.ftz.f32 	%f210, %f209, %f202;
	fma.rn.ftz.f32 	%f29, %f168, %f187, %f210;
	mul.ftz.f32 	%f211, %f209, %f205;
	fma.rn.ftz.f32 	%f30, %f168, %f189, %f211;
	mul.ftz.f32 	%f212, %f209, %f208;
	fma.rn.ftz.f32 	%f31, %f168, %f191, %f212;
	mad.lo.s32 	%r21, %r3, %r4, %r2;
	cvt.s64.s32	%rd1, %r21;
	setp.eq.s32	%p11, %r5, 0;
	@%p11 bra 	BB0_14;

	cvta.to.global.u64 	%rd29, %rd2;
	shl.b64 	%rd30, %rd1, 4;
	add.s64 	%rd31, %rd29, %rd30;
	st.global.v4.f32 	[%rd31], {%f31, %f30, %f29, %f99};
	bra.uni 	BB0_15;

BB0_14:
	cvta.to.global.u64 	%rd32, %rd2;
	shl.b64 	%rd33, %rd1, 3;
	add.s64 	%rd34, %rd32, %rd33;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f99;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f29;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f30;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f31;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd34], {%rs4, %rs3, %rs2, %rs1};

BB0_15:
	ret;
}


