//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_SecondaryPass3$__cuda_local_var_180674_474_non_const_p_local has been demoted

.visible .entry ShaderKernel_SecondaryPass3(
	.param .u64 ShaderKernel_SecondaryPass3_param_0,
	.param .u32 ShaderKernel_SecondaryPass3_param_1,
	.param .u32 ShaderKernel_SecondaryPass3_param_2,
	.param .u32 ShaderKernel_SecondaryPass3_param_3,
	.param .u32 ShaderKernel_SecondaryPass3_param_4,
	.param .u64 ShaderKernel_SecondaryPass3_param_5,
	.param .u64 ShaderKernel_SecondaryPass3_param_6
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<92>;
	.reg .s64 	%rd<32>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_SecondaryPass3$__cuda_local_var_180674_474_non_const_p_local[32];

	ld.param.u64 	%rd4, [ShaderKernel_SecondaryPass3_param_0];
	ld.param.u32 	%r4, [ShaderKernel_SecondaryPass3_param_1];
	ld.param.u32 	%r5, [ShaderKernel_SecondaryPass3_param_2];
	ld.param.u32 	%r6, [ShaderKernel_SecondaryPass3_param_3];
	ld.param.u32 	%r7, [ShaderKernel_SecondaryPass3_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_SecondaryPass3_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 1;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_SecondaryPass3$__cuda_local_var_180674_474_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd5, %rd6;
	ld.global.v4.f32 	{%f7, %f8, %f9, %f10}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f7, %f8, %f9, %f10};

BB0_3:
	cvt.rn.f32.s32	%f15, %r2;
	add.ftz.f32 	%f1, %f15, 0f3F000000;
	cvt.rn.f32.s32	%f16, %r3;
	add.ftz.f32 	%f2, %f16, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	add.ftz.f32 	%f70, %f2, 0f00000000;
	add.ftz.f32 	%f27, %f1, 0f3F800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [texture0_RECT, {%f27, %f70}];
	// inline asm
	add.ftz.f32 	%f33, %f1, 0f40000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [texture0_RECT, {%f33, %f70}];
	// inline asm
	add.ftz.f32 	%f39, %f1, 0f40400000;
	// inline asm
	tex.2d.v4.f32.f32 {%f35, %f36, %f37, %f38}, [texture0_RECT, {%f39, %f70}];
	// inline asm
	add.ftz.f32 	%f45, %f1, 0f40800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f41, %f42, %f43, %f44}, [texture0_RECT, {%f45, %f70}];
	// inline asm
	ld.shared.v4.f32 	{%f71, %f72, %f73, %f74}, [ShaderKernel_SecondaryPass3$__cuda_local_var_180674_474_non_const_p_local];
	mul.ftz.f32 	%f76, %f26, %f71;
	mul.ftz.f32 	%f78, %f32, %f72;
	mul.ftz.f32 	%f80, %f38, %f73;
	mul.ftz.f32 	%f82, %f44, %f74;
	add.ftz.f32 	%f51, %f1, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f47, %f48, %f49, %f50}, [texture0_RECT, {%f51, %f70}];
	// inline asm
	add.ftz.f32 	%f57, %f1, 0fC0000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f53, %f54, %f55, %f56}, [texture0_RECT, {%f57, %f70}];
	// inline asm
	add.ftz.f32 	%f63, %f1, 0fC0400000;
	// inline asm
	tex.2d.v4.f32.f32 {%f59, %f60, %f61, %f62}, [texture0_RECT, {%f63, %f70}];
	// inline asm
	add.ftz.f32 	%f69, %f1, 0fC0800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f65, %f66, %f67, %f68}, [texture0_RECT, {%f69, %f70}];
	// inline asm
	fma.rn.ftz.f32 	%f83, %f50, %f71, %f76;
	fma.rn.ftz.f32 	%f84, %f56, %f72, %f78;
	fma.rn.ftz.f32 	%f85, %f62, %f73, %f80;
	fma.rn.ftz.f32 	%f86, %f68, %f74, %f82;
	add.ftz.f32 	%f87, %f83, %f84;
	add.ftz.f32 	%f88, %f87, %f85;
	add.ftz.f32 	%f89, %f88, %f86;
	add.ftz.f32 	%f90, %f89, %f20;
	ld.shared.f32 	%f91, [ShaderKernel_SecondaryPass3$__cuda_local_var_180674_474_non_const_p_local+28];
	mul.ftz.f32 	%f6, %f90, %f91;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p5, %r5, 0;
	@%p5 bra 	BB0_5;

	shl.b64 	%rd28, %rd2, 4;
	add.s64 	%rd29, %rd1, %rd28;
	st.global.v4.f32 	[%rd29], {%f17, %f18, %f19, %f6};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd30, %rd2, 3;
	add.s64 	%rd31, %rd1, %rd30;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f6;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f18;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f17;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd31], {%rs4, %rs3, %rs2, %rs1};

BB0_6:
	ret;
}


