//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref inSrcTexture;

.visible .entry RemoveFlickerKernel(
	.param .u64 RemoveFlickerKernel_param_0,
	.param .u64 RemoveFlickerKernel_param_1,
	.param .u32 RemoveFlickerKernel_param_2,
	.param .u32 RemoveFlickerKernel_param_3,
	.param .u32 RemoveFlickerKernel_param_4,
	.param .u32 RemoveFlickerKernel_param_5
)
{
	.reg .pred 	%p<8>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<15>;
	.reg .f32 	%f<54>;
	.reg .s64 	%rd<13>;


	ld.param.u64 	%rd3, [RemoveFlickerKernel_param_1];
	ld.param.u32 	%r3, [RemoveFlickerKernel_param_2];
	ld.param.u32 	%r4, [RemoveFlickerKernel_param_3];
	ld.param.u32 	%r6, [RemoveFlickerKernel_param_4];
	ld.param.u32 	%r5, [RemoveFlickerKernel_param_5];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r5;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f29, %r1;
	add.ftz.f32 	%f27, %f29, 0f3F000000;
	cvt.rn.f32.s32	%f2, %r2;
	add.ftz.f32 	%f28, %f2, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [inSrcTexture, {%f27, %f28}];
	// inline asm
	add.s32 	%r13, %r5, -1;
	setp.ne.s32	%p4, %r2, %r13;
	setp.ne.s32	%p5, %r2, 0;
	and.pred  	%p6, %p4, %p5;
	mov.f32 	%f53, %f26;
	mov.f32 	%f52, %f25;
	mov.f32 	%f51, %f24;
	mov.f32 	%f50, %f23;
	@!%p6 bra 	BB0_3;
	bra.uni 	BB0_2;

BB0_2:
	add.ftz.f32 	%f35, %f2, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f30, %f31, %f32, %f33}, [inSrcTexture, {%f27, %f35}];
	// inline asm
	add.ftz.f32 	%f41, %f2, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f36, %f37, %f38, %f39}, [inSrcTexture, {%f27, %f41}];
	// inline asm
	add.ftz.f32 	%f42, %f30, %f36;
	add.ftz.f32 	%f43, %f31, %f37;
	add.ftz.f32 	%f44, %f32, %f38;
	add.ftz.f32 	%f45, %f33, %f39;
	mul.ftz.f32 	%f46, %f42, 0f3E800000;
	mul.ftz.f32 	%f47, %f43, 0f3E800000;
	mul.ftz.f32 	%f48, %f44, 0f3E800000;
	mul.ftz.f32 	%f49, %f45, 0f3E800000;
	fma.rn.ftz.f32 	%f50, %f23, 0f3F000000, %f46;
	fma.rn.ftz.f32 	%f51, %f24, 0f3F000000, %f47;
	fma.rn.ftz.f32 	%f52, %f25, 0f3F000000, %f48;
	fma.rn.ftz.f32 	%f53, %f26, 0f3F000000, %f49;

BB0_3:
	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32	%rd2, %r14;
	setp.eq.s32	%p7, %r4, 0;
	@%p7 bra 	BB0_5;

	shl.b64 	%rd9, %rd2, 4;
	add.s64 	%rd10, %rd1, %rd9;
	st.global.v4.f32 	[%rd10], {%f50, %f51, %f52, %f53};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd11, %rd2, 3;
	add.s64 	%rd12, %rd1, %rd11;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f53;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f52;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f51;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f50;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd12], {%rs4, %rs3, %rs2, %rs1};

BB0_6:
	ret;
}


