//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
.global .texref texture2_2D;
// ShaderKernel_PrimaryRGBCurves$__cuda_local_var_180673_569_non_const_p_local has been demoted

.visible .entry ShaderKernel_PrimaryRGBCurves(
	.param .u64 ShaderKernel_PrimaryRGBCurves_param_0,
	.param .u32 ShaderKernel_PrimaryRGBCurves_param_1,
	.param .u32 ShaderKernel_PrimaryRGBCurves_param_2,
	.param .u32 ShaderKernel_PrimaryRGBCurves_param_3,
	.param .u32 ShaderKernel_PrimaryRGBCurves_param_4,
	.param .u64 ShaderKernel_PrimaryRGBCurves_param_5,
	.param .u64 ShaderKernel_PrimaryRGBCurves_param_6,
	.param .u64 ShaderKernel_PrimaryRGBCurves_param_7
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<70>;
	.reg .s64 	%rd<20>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_PrimaryRGBCurves$__cuda_local_var_180673_569_non_const_p_local[16];

	ld.param.u64 	%rd4, [ShaderKernel_PrimaryRGBCurves_param_0];
	ld.param.u32 	%r4, [ShaderKernel_PrimaryRGBCurves_param_1];
	ld.param.u32 	%r5, [ShaderKernel_PrimaryRGBCurves_param_2];
	ld.param.u32 	%r6, [ShaderKernel_PrimaryRGBCurves_param_3];
	ld.param.u32 	%r7, [ShaderKernel_PrimaryRGBCurves_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_PrimaryRGBCurves_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	ld.global.v4.f32 	{%f7, %f8, %f9, %f10}, [%rd5];
	st.shared.v4.f32 	[ShaderKernel_PrimaryRGBCurves$__cuda_local_var_180673_569_non_const_p_local], {%f7, %f8, %f9, %f10};

BB0_3:
	cvt.rn.f32.s32	%f15, %r2;
	add.ftz.f32 	%f1, %f15, 0f3F000000;
	cvt.rn.f32.s32	%f16, %r3;
	add.ftz.f32 	%f2, %f16, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	cvt.ftz.sat.f32.f32	%f47, %f19;
	cvt.ftz.sat.f32.f32	%f48, %f18;
	cvt.ftz.sat.f32.f32	%f49, %f17;
	cvt.ftz.sat.f32.f32	%f3, %f20;
	ld.shared.v4.f32 	{%f50, %f51, %f52, %f53}, [ShaderKernel_PrimaryRGBCurves$__cuda_local_var_180673_569_non_const_p_local];
	mul.ftz.f32 	%f55, %f48, %f51;
	fma.rn.ftz.f32 	%f57, %f47, %f50, %f55;
	fma.rn.ftz.f32 	%f59, %f49, %f52, %f57;
	fma.rn.ftz.f32 	%f27, %f59, 0f3F7FF000, 0f3A000000;
	mov.f32 	%f46, 0f3D800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [texture2_2D, {%f27, %f46}];
	// inline asm
	setp.gt.ftz.f32	%p5, %f27, 0f322BCC77;
	selp.f32	%f60, %f27, 0f322BCC77, %p5;
	mov.f32 	%f61, 0f3F800000;
	div.rn.ftz.f32 	%f62, %f61, %f60;
	mul.ftz.f32 	%f63, %f62, %f26;
	mul.ftz.f32 	%f64, %f63, %f47;
	cvt.ftz.sat.f32.f32	%f65, %f64;
	mul.ftz.f32 	%f66, %f63, %f48;
	cvt.ftz.sat.f32.f32	%f67, %f66;
	mul.ftz.f32 	%f68, %f63, %f49;
	cvt.ftz.sat.f32.f32	%f69, %f68;
	fma.rn.ftz.f32 	%f33, %f65, 0f3F7FF000, 0f3A000000;
	fma.rn.ftz.f32 	%f39, %f67, 0f3F7FF000, 0f3A000000;
	fma.rn.ftz.f32 	%f45, %f69, 0f3F7FF000, 0f3A000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [texture2_2D, {%f33, %f46}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f35, %f36, %f37, %f38}, [texture2_2D, {%f39, %f46}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f41, %f42, %f43, %f44}, [texture2_2D, {%f45, %f46}];
	// inline asm
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p6, %r5, 0;
	@%p6 bra 	BB0_5;

	shl.b64 	%rd16, %rd2, 4;
	add.s64 	%rd17, %rd1, %rd16;
	st.global.v4.f32 	[%rd17], {%f43, %f36, %f29, %f3};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd18, %rd2, 3;
	add.s64 	%rd19, %rd1, %rd18;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f29;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f36;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f43;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd19], {%rs4, %rs3, %rs2, %rs1};

BB0_6:
	ret;
}


