//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry CopyMemory2DKernel(
	.param .u64 CopyMemory2DKernel_param_0,
	.param .u32 CopyMemory2DKernel_param_1,
	.param .u32 CopyMemory2DKernel_param_2,
	.param .u64 CopyMemory2DKernel_param_3,
	.param .u32 CopyMemory2DKernel_param_4,
	.param .u32 CopyMemory2DKernel_param_5,
	.param .u32 CopyMemory2DKernel_param_6,
	.param .u32 CopyMemory2DKernel_param_7,
	.param .u32 CopyMemory2DKernel_param_8
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<16>;
	.reg .f32 	%f<21>;
	.reg .s64 	%rd<23>;


	ld.param.u64 	%rd8, [CopyMemory2DKernel_param_0];
	ld.param.u32 	%r3, [CopyMemory2DKernel_param_1];
	ld.param.u64 	%rd9, [CopyMemory2DKernel_param_3];
	ld.param.u32 	%r4, [CopyMemory2DKernel_param_4];
	ld.param.u32 	%r5, [CopyMemory2DKernel_param_6];
	ld.param.u32 	%r6, [CopyMemory2DKernel_param_7];
	ld.param.u32 	%r7, [CopyMemory2DKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd9;
	cvta.to.global.u64 	%rd2, %rd8;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	ld.param.s32 	%rd3, [CopyMemory2DKernel_param_2];
	ld.param.s32 	%rd4, [CopyMemory2DKernel_param_5];
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	shl.b64 	%rd10, %rd4, 4;
	add.s64 	%rd5, %rd1, %rd10;
	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32	%rd6, %r14;
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB0_3;

	add.s64 	%rd11, %rd6, %rd3;
	shl.b64 	%rd12, %rd11, 4;
	add.s64 	%rd13, %rd2, %rd12;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd13];
	mov.f32 	%f20, %f16;
	mov.f32 	%f19, %f15;
	mov.f32 	%f18, %f14;
	mov.f32 	%f17, %f13;
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd14, %rd3, 4;
	add.s64 	%rd15, %rd2, %rd14;
	shl.b64 	%rd16, %rd6, 3;
	add.s64 	%rd17, %rd15, %rd16;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd17];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f17, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f18, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f19, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f20, %temp;
	}

BB0_4:
	mad.lo.s32 	%r15, %r2, %r4, %r1;
	cvt.s64.s32	%rd7, %r15;
	@%p4 bra 	BB0_6;

	add.s64 	%rd18, %rd7, %rd4;
	shl.b64 	%rd19, %rd18, 4;
	add.s64 	%rd20, %rd1, %rd19;
	st.global.v4.f32 	[%rd20], {%f17, %f18, %f19, %f20};
	bra.uni 	BB0_7;

BB0_6:
	shl.b64 	%rd21, %rd7, 3;
	add.s64 	%rd22, %rd5, %rd21;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f17;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f18;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd22], {%rs9, %rs10, %rs11, %rs12};

BB0_7:
	ret;
}

.visible .entry CopyRectKernel(
	.param .u64 CopyRectKernel_param_0,
	.param .u32 CopyRectKernel_param_1,
	.param .u64 CopyRectKernel_param_2,
	.param .u32 CopyRectKernel_param_3,
	.param .u32 CopyRectKernel_param_4,
	.param .u32 CopyRectKernel_param_5,
	.param .u32 CopyRectKernel_param_6,
	.param .u32 CopyRectKernel_param_7,
	.param .u32 CopyRectKernel_param_8,
	.param .u32 CopyRectKernel_param_9,
	.param .u32 CopyRectKernel_param_10
)
{
	.reg .pred 	%p<9>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<26>;
	.reg .f32 	%f<21>;
	.reg .s64 	%rd<15>;


	ld.param.u64 	%rd5, [CopyRectKernel_param_0];
	ld.param.u32 	%r5, [CopyRectKernel_param_1];
	ld.param.u64 	%rd6, [CopyRectKernel_param_2];
	ld.param.u32 	%r6, [CopyRectKernel_param_3];
	ld.param.u32 	%r7, [CopyRectKernel_param_4];
	ld.param.u32 	%r8, [CopyRectKernel_param_5];
	ld.param.u32 	%r9, [CopyRectKernel_param_6];
	ld.param.u32 	%r12, [CopyRectKernel_param_7];
	ld.param.u32 	%r10, [CopyRectKernel_param_8];
	ld.param.u32 	%r13, [CopyRectKernel_param_9];
	ld.param.u32 	%r11, [CopyRectKernel_param_10];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r14, %ntid.x;
	mov.u32 	%r15, %ctaid.x;
	mov.u32 	%r16, %tid.x;
	mad.lo.s32 	%r1, %r14, %r15, %r16;
	add.s32 	%r2, %r1, %r12;
	mov.u32 	%r17, %ntid.y;
	mov.u32 	%r18, %ctaid.y;
	mov.u32 	%r19, %tid.y;
	mad.lo.s32 	%r3, %r17, %r18, %r19;
	add.s32 	%r4, %r3, %r10;
	setp.gt.s32	%p1, %r1, -1;
	add.s32 	%r20, %r13, %r12;
	setp.lt.s32	%p2, %r2, %r20;
	and.pred  	%p3, %p1, %p2;
	setp.gt.s32	%p4, %r3, -1;
	and.pred  	%p5, %p3, %p4;
	@!%p5 bra 	BB1_8;
	bra.uni 	BB1_1;

BB1_1:
	add.s32 	%r21, %r11, %r10;
	setp.ge.s32	%p6, %r4, %r21;
	@%p6 bra 	BB1_8;

	add.s32 	%r22, %r3, %r9;
	add.s32 	%r23, %r1, %r8;
	mad.lo.s32 	%r24, %r22, %r5, %r23;
	cvt.s64.s32	%rd3, %r24;
	setp.eq.s32	%p7, %r7, 0;
	@%p7 bra 	BB1_4;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd8];
	mov.f32 	%f20, %f16;
	mov.f32 	%f19, %f15;
	mov.f32 	%f18, %f14;
	mov.f32 	%f17, %f13;
	bra.uni 	BB1_5;

BB1_4:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f17, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f18, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f19, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f20, %temp;
	}

BB1_5:
	mad.lo.s32 	%r25, %r4, %r6, %r2;
	cvt.s64.s32	%rd4, %r25;
	@%p7 bra 	BB1_7;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f17, %f18, %f19, %f20};
	bra.uni 	BB1_8;

BB1_7:
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f17;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f18;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs9, %rs10, %rs11, %rs12};

BB1_8:
	ret;
}


