//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_Linearize$__cuda_local_var_180673_469_non_const_p_local has been demoted

.visible .entry ShaderKernel_Linearize(
	.param .u64 ShaderKernel_Linearize_param_0,
	.param .u32 ShaderKernel_Linearize_param_1,
	.param .u32 ShaderKernel_Linearize_param_2,
	.param .u32 ShaderKernel_Linearize_param_3,
	.param .u32 ShaderKernel_Linearize_param_4,
	.param .u64 ShaderKernel_Linearize_param_5,
	.param .u64 ShaderKernel_Linearize_param_6
)
{
	.reg .pred 	%p<12>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<60>;
	.reg .s64 	%rd<12>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_Linearize$__cuda_local_var_180673_469_non_const_p_local[16];

	ld.param.u64 	%rd2, [ShaderKernel_Linearize_param_0];
	ld.param.u32 	%r4, [ShaderKernel_Linearize_param_1];
	ld.param.u32 	%r5, [ShaderKernel_Linearize_param_2];
	ld.param.u32 	%r6, [ShaderKernel_Linearize_param_3];
	ld.param.u32 	%r7, [ShaderKernel_Linearize_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_Linearize_param_5];
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_15;
	bra.uni 	BB0_1;

BB0_1:
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd4, %rd3;
	ld.global.v4.f32 	{%f25, %f26, %f27, %f28}, [%rd4];
	st.shared.v4.f32 	[ShaderKernel_Linearize$__cuda_local_var_180673_469_non_const_p_local], {%f25, %f26, %f27, %f28};

BB0_3:
	cvt.rn.f32.s32	%f33, %r2;
	add.ftz.f32 	%f1, %f33, 0f3F000000;
	cvt.rn.f32.s32	%f34, %r3;
	add.ftz.f32 	%f2, %f34, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f35, %f36, %f37, %f38}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	abs.ftz.f32 	%f7, %f37;
	abs.ftz.f32 	%f8, %f36;
	abs.ftz.f32 	%f9, %f35;
	cvt.ftz.sat.f32.f32	%f10, %f7;
	cvt.ftz.sat.f32.f32	%f11, %f8;
	cvt.ftz.sat.f32.f32	%f12, %f9;
	ld.shared.f32 	%f13, [ShaderKernel_Linearize$__cuda_local_var_180673_469_non_const_p_local];
	setp.gtu.ftz.f32	%p5, %f10, 0f00000000;
	@%p5 bra 	BB0_5;

	mov.f32 	%f57, 0f00000000;
	bra.uni 	BB0_6;

BB0_5:
	lg2.approx.ftz.f32 	%f42, %f10;
	mul.ftz.f32 	%f43, %f42, %f13;
	ex2.approx.ftz.f32 	%f57, %f43;

BB0_6:
	sub.ftz.f32 	%f16, %f7, %f10;
	setp.gtu.ftz.f32	%p6, %f11, 0f00000000;
	@%p6 bra 	BB0_8;

	mov.f32 	%f58, 0f00000000;
	bra.uni 	BB0_9;

BB0_8:
	lg2.approx.ftz.f32 	%f45, %f11;
	mul.ftz.f32 	%f46, %f45, %f13;
	ex2.approx.ftz.f32 	%f58, %f46;

BB0_9:
	sub.ftz.f32 	%f19, %f8, %f11;
	setp.gtu.ftz.f32	%p7, %f12, 0f00000000;
	@%p7 bra 	BB0_11;

	mov.f32 	%f59, 0f00000000;
	bra.uni 	BB0_12;

BB0_11:
	lg2.approx.ftz.f32 	%f48, %f12;
	mul.ftz.f32 	%f49, %f48, %f13;
	ex2.approx.ftz.f32 	%f59, %f49;

BB0_12:
	sub.ftz.f32 	%f50, %f9, %f12;
	fma.rn.ftz.f32 	%f51, %f16, %f57, %f57;
	fma.rn.ftz.f32 	%f52, %f19, %f58, %f58;
	fma.rn.ftz.f32 	%f53, %f50, %f59, %f59;
	setp.lt.ftz.f32	%p8, %f37, 0f00000000;
	selp.f32	%f54, 0fBF800000, 0f3F800000, %p8;
	mul.ftz.f32 	%f22, %f51, %f54;
	setp.lt.ftz.f32	%p9, %f36, 0f00000000;
	selp.f32	%f55, 0fBF800000, 0f3F800000, %p9;
	mul.ftz.f32 	%f23, %f52, %f55;
	setp.lt.ftz.f32	%p10, %f35, 0f00000000;
	selp.f32	%f56, 0fBF800000, 0f3F800000, %p10;
	mul.ftz.f32 	%f24, %f53, %f56;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd1, %r13;
	setp.eq.s32	%p11, %r5, 0;
	@%p11 bra 	BB0_14;

	cvta.to.global.u64 	%rd6, %rd2;
	shl.b64 	%rd7, %rd1, 4;
	add.s64 	%rd8, %rd6, %rd7;
	st.global.v4.f32 	[%rd8], {%f24, %f23, %f22, %f38};
	bra.uni 	BB0_15;

BB0_14:
	cvta.to.global.u64 	%rd9, %rd2;
	shl.b64 	%rd10, %rd1, 3;
	add.s64 	%rd11, %rd9, %rd10;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f23;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f24;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f38;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd11], {%rs3, %rs2, %rs1, %rs4};

BB0_15:
	ret;
}


