//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local has been demoted

.visible .entry ShaderKernel_IRIDASSimplePrimary(
	.param .u64 ShaderKernel_IRIDASSimplePrimary_param_0,
	.param .u32 ShaderKernel_IRIDASSimplePrimary_param_1,
	.param .u32 ShaderKernel_IRIDASSimplePrimary_param_2,
	.param .u32 ShaderKernel_IRIDASSimplePrimary_param_3,
	.param .u32 ShaderKernel_IRIDASSimplePrimary_param_4,
	.param .u64 ShaderKernel_IRIDASSimplePrimary_param_5,
	.param .u64 ShaderKernel_IRIDASSimplePrimary_param_6,
	.param .u64 ShaderKernel_IRIDASSimplePrimary_param_7
)
{
	.reg .pred 	%p<15>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<17>;
	.reg .f32 	%f<155>;
	.reg .s64 	%rd<20>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local[128];

	ld.param.u64 	%rd4, [ShaderKernel_IRIDASSimplePrimary_param_0];
	ld.param.u32 	%r4, [ShaderKernel_IRIDASSimplePrimary_param_1];
	ld.param.u32 	%r5, [ShaderKernel_IRIDASSimplePrimary_param_2];
	ld.param.u32 	%r6, [ShaderKernel_IRIDASSimplePrimary_param_3];
	ld.param.u32 	%r7, [ShaderKernel_IRIDASSimplePrimary_param_4];
	ld.param.u64 	%rd5, [ShaderKernel_IRIDASSimplePrimary_param_5];
	ld.param.u64 	%rd6, [ShaderKernel_IRIDASSimplePrimary_param_7];
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_21;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 7;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd7, %rd5;
	mul.wide.u32 	%rd8, %r1, 16;
	mov.u64 	%rd9, ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local;
	add.s64 	%rd10, %rd9, %rd8;
	add.s64 	%rd11, %rd7, %rd8;
	ld.global.v4.f32 	{%f44, %f45, %f46, %f47}, [%rd11];
	st.shared.v4.f32 	[%rd10], {%f44, %f45, %f46, %f47};

BB0_3:
	cvta.to.global.u64 	%rd1, %rd6;
	cvt.rn.f32.s32	%f52, %r2;
	add.ftz.f32 	%f1, %f52, 0f3F000000;
	cvt.rn.f32.s32	%f53, %r3;
	add.ftz.f32 	%f2, %f53, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f54, %f55, %f56, %f57}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	ld.global.u32 	%r13, [%rd1+4];
	setp.eq.s32	%p5, %r13, 0;
	mov.f32 	%f143, %f56;
	mov.f32 	%f144, %f55;
	mov.f32 	%f145, %f54;
	@%p5 bra 	BB0_5;

	ld.shared.v4.f32 	{%f60, %f61, %f62, %f63}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+64];
	mul.ftz.f32 	%f65, %f55, %f61;
	fma.rn.ftz.f32 	%f67, %f56, %f60, %f65;
	fma.rn.ftz.f32 	%f69, %f54, %f62, %f67;
	sub.ftz.f32 	%f70, %f56, %f69;
	sub.ftz.f32 	%f71, %f55, %f69;
	sub.ftz.f32 	%f72, %f54, %f69;
	ld.shared.v4.f32 	{%f73, %f74, %f75, %f76}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+80];
	fma.rn.ftz.f32 	%f143, %f70, %f73, %f69;
	fma.rn.ftz.f32 	%f144, %f71, %f74, %f69;
	fma.rn.ftz.f32 	%f145, %f72, %f75, %f69;

BB0_5:
	ld.shared.v4.f32 	{%f80, %f81, %f82, %f83}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local];
	ld.shared.v4.f32 	{%f84, %f85, %f86, %f87}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+16];
	fma.rn.ftz.f32 	%f149, %f143, %f80, %f84;
	fma.rn.ftz.f32 	%f150, %f144, %f81, %f85;
	fma.rn.ftz.f32 	%f151, %f145, %f82, %f86;
	ld.global.u32 	%r14, [%rd1];
	setp.eq.s32	%p6, %r14, 0;
	@%p6 bra 	BB0_16;

	abs.ftz.f32 	%f19, %f150;
	abs.ftz.f32 	%f20, %f151;
	abs.ftz.f32 	%f21, %f149;
	setp.gtu.ftz.f32	%p7, %f21, 0f00000000;
	@%p7 bra 	BB0_8;

	mov.f32 	%f146, 0f00000000;
	bra.uni 	BB0_9;

BB0_8:
	ld.shared.f32 	%f95, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+112];
	lg2.approx.ftz.f32 	%f96, %f21;
	mul.ftz.f32 	%f97, %f96, %f95;
	ex2.approx.ftz.f32 	%f146, %f97;

BB0_9:
	setp.gtu.ftz.f32	%p8, %f19, 0f00000000;
	@%p8 bra 	BB0_11;

	mov.f32 	%f147, 0f00000000;
	bra.uni 	BB0_12;

BB0_11:
	ld.shared.f32 	%f99, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+116];
	lg2.approx.ftz.f32 	%f100, %f19;
	mul.ftz.f32 	%f101, %f100, %f99;
	ex2.approx.ftz.f32 	%f147, %f101;

BB0_12:
	setp.gtu.ftz.f32	%p9, %f20, 0f00000000;
	@%p9 bra 	BB0_14;

	mov.f32 	%f148, 0f00000000;
	bra.uni 	BB0_15;

BB0_14:
	ld.shared.f32 	%f103, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+120];
	lg2.approx.ftz.f32 	%f104, %f20;
	mul.ftz.f32 	%f105, %f104, %f103;
	ex2.approx.ftz.f32 	%f148, %f105;

BB0_15:
	setp.lt.ftz.f32	%p10, %f149, 0f00000000;
	selp.f32	%f106, 0fBF800000, 0f3F800000, %p10;
	setp.lt.ftz.f32	%p11, %f150, 0f00000000;
	selp.f32	%f107, 0fBF800000, 0f3F800000, %p11;
	setp.lt.ftz.f32	%p12, %f151, 0f00000000;
	selp.f32	%f108, 0fBF800000, 0f3F800000, %p12;
	mul.ftz.f32 	%f149, %f146, %f106;
	mul.ftz.f32 	%f150, %f147, %f107;
	mul.ftz.f32 	%f151, %f148, %f108;

BB0_16:
	ld.shared.v4.f32 	{%f109, %f110, %f111, %f112}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+32];
	ld.shared.v4.f32 	{%f113, %f114, %f115, %f116}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+48];
	fma.rn.ftz.f32 	%f152, %f149, %f109, %f113;
	fma.rn.ftz.f32 	%f153, %f150, %f110, %f114;
	fma.rn.ftz.f32 	%f154, %f151, %f111, %f115;
	ld.global.u32 	%r15, [%rd1+8];
	setp.eq.s32	%p13, %r15, 0;
	@%p13 bra 	BB0_18;

	ld.shared.v4.f32 	{%f123, %f124, %f125, %f126}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+64];
	mul.ftz.f32 	%f128, %f153, %f124;
	fma.rn.ftz.f32 	%f130, %f152, %f123, %f128;
	fma.rn.ftz.f32 	%f132, %f154, %f125, %f130;
	sub.ftz.f32 	%f133, %f152, %f132;
	sub.ftz.f32 	%f134, %f153, %f132;
	sub.ftz.f32 	%f135, %f154, %f132;
	ld.shared.v4.f32 	{%f136, %f137, %f138, %f139}, [ShaderKernel_IRIDASSimplePrimary$__cuda_local_var_180692_497_non_const_p_local+96];
	fma.rn.ftz.f32 	%f152, %f133, %f136, %f132;
	fma.rn.ftz.f32 	%f153, %f134, %f137, %f132;
	fma.rn.ftz.f32 	%f154, %f135, %f138, %f132;

BB0_18:
	mad.lo.s32 	%r16, %r3, %r4, %r2;
	cvt.s64.s32	%rd3, %r16;
	setp.eq.s32	%p14, %r5, 0;
	@%p14 bra 	BB0_20;

	cvta.to.global.u64 	%rd14, %rd4;
	shl.b64 	%rd15, %rd3, 4;
	add.s64 	%rd16, %rd14, %rd15;
	st.global.v4.f32 	[%rd16], {%f154, %f153, %f152, %f57};
	bra.uni 	BB0_21;

BB0_20:
	cvta.to.global.u64 	%rd17, %rd4;
	shl.b64 	%rd18, %rd3, 3;
	add.s64 	%rd19, %rd17, %rd18;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f57;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f152;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f153;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f154;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd19], {%rs4, %rs3, %rs2, %rs1};

BB0_21:
	ret;
}


