//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry InvertAlphaKernel(
	.param .u64 InvertAlphaKernel_param_0,
	.param .u32 InvertAlphaKernel_param_1,
	.param .u32 InvertAlphaKernel_param_2,
	.param .u32 InvertAlphaKernel_param_3,
	.param .u32 InvertAlphaKernel_param_4
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<24>;
	.reg .s64 	%rd<7>;


	ld.param.u64 	%rd3, [InvertAlphaKernel_param_0];
	ld.param.u32 	%r3, [InvertAlphaKernel_param_1];
	ld.param.u32 	%r4, [InvertAlphaKernel_param_2];
	ld.param.u32 	%r5, [InvertAlphaKernel_param_3];
	ld.param.u32 	%r6, [InvertAlphaKernel_param_4];
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	cvta.to.global.u64 	%rd4, %rd3;
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	mul.wide.s32 	%rd5, %r13, 16;
	add.s64 	%rd1, %rd4, %rd5;
	mul.wide.s32 	%rd6, %r13, 8;
	add.s64 	%rd2, %rd4, %rd6;
	setp.eq.s32	%p4, %r4, 0;
	@%p4 bra 	BB0_3;

	ld.global.v4.f32 	{%f14, %f15, %f16, %f17}, [%rd1];
	mov.f32 	%f23, %f17;
	mov.f32 	%f22, %f16;
	mov.f32 	%f21, %f15;
	mov.f32 	%f20, %f14;
	bra.uni 	BB0_4;

BB0_3:
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd2];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f20, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f21, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f22, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f23, %temp;
	}

BB0_4:
	cvt.ftz.sat.f32.f32	%f18, %f23;
	mov.f32 	%f19, 0f3F800000;
	sub.ftz.f32 	%f13, %f19, %f18;
	@%p4 bra 	BB0_6;

	st.global.v4.f32 	[%rd1], {%f20, %f21, %f22, %f13};
	bra.uni 	BB0_7;

BB0_6:
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f13;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f21;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd2], {%rs10, %rs11, %rs12, %rs9};

BB0_7:
	ret;
}


