//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
.global .texref texture1_RECT;
// ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local has been demoted

.visible .entry ShaderKernel_GaussianBlurRange(
	.param .u64 ShaderKernel_GaussianBlurRange_param_0,
	.param .u32 ShaderKernel_GaussianBlurRange_param_1,
	.param .u32 ShaderKernel_GaussianBlurRange_param_2,
	.param .u32 ShaderKernel_GaussianBlurRange_param_3,
	.param .u32 ShaderKernel_GaussianBlurRange_param_4,
	.param .u64 ShaderKernel_GaussianBlurRange_param_5,
	.param .u64 ShaderKernel_GaussianBlurRange_param_6,
	.param .u64 ShaderKernel_GaussianBlurRange_param_7
)
{
	.reg .pred 	%p<14>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<343>;
	.reg .s64 	%rd<50>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local[192];

	ld.param.u64 	%rd4, [ShaderKernel_GaussianBlurRange_param_0];
	ld.param.u32 	%r4, [ShaderKernel_GaussianBlurRange_param_1];
	ld.param.u32 	%r5, [ShaderKernel_GaussianBlurRange_param_2];
	ld.param.u32 	%r6, [ShaderKernel_GaussianBlurRange_param_3];
	ld.param.u32 	%r7, [ShaderKernel_GaussianBlurRange_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_GaussianBlurRange_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 11;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd5, %rd6;
	ld.global.v4.f32 	{%f7, %f8, %f9, %f10}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f7, %f8, %f9, %f10};

BB0_3:
	cvt.rn.f32.s32	%f15, %r2;
	add.ftz.f32 	%f1, %f15, 0f3F000000;
	cvt.rn.f32.s32	%f16, %r3;
	add.ftz.f32 	%f2, %f16, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [texture1_RECT, {%f1, %f2}];
	// inline asm
	ld.shared.v4.f32 	{%f125, %f126, %f127, %f128}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+128];
	mul.ftz.f32 	%f130, %f19, %f125;
	mul.ftz.f32 	%f132, %f18, %f126;
	mul.ftz.f32 	%f134, %f17, %f127;
	add.ftz.f32 	%f88, %f2, 0f3F800000;
	mov.f32 	%f135, 0f3F800000;
	add.ftz.f32 	%f51, %f1, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [texture1_RECT, {%f51, %f88}];
	// inline asm
	ld.shared.v4.f32 	{%f136, %f137, %f138, %f139}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+160];
	fma.rn.ftz.f32 	%f141, %f25, %f136, %f130;
	fma.rn.ftz.f32 	%f143, %f24, %f137, %f132;
	fma.rn.ftz.f32 	%f145, %f23, %f138, %f134;
	add.ftz.f32 	%f57, %f1, 0f3F800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [texture1_RECT, {%f57, %f88}];
	// inline asm
	fma.rn.ftz.f32 	%f146, %f31, %f136, %f141;
	fma.rn.ftz.f32 	%f147, %f30, %f137, %f143;
	fma.rn.ftz.f32 	%f148, %f29, %f138, %f145;
	add.ftz.f32 	%f82, %f2, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f35, %f36, %f37, %f38}, [texture1_RECT, {%f51, %f82}];
	// inline asm
	fma.rn.ftz.f32 	%f149, %f37, %f136, %f146;
	fma.rn.ftz.f32 	%f150, %f36, %f137, %f147;
	fma.rn.ftz.f32 	%f151, %f35, %f138, %f148;
	// inline asm
	tex.2d.v4.f32.f32 {%f41, %f42, %f43, %f44}, [texture1_RECT, {%f57, %f82}];
	// inline asm
	fma.rn.ftz.f32 	%f152, %f43, %f136, %f149;
	fma.rn.ftz.f32 	%f153, %f42, %f137, %f150;
	fma.rn.ftz.f32 	%f154, %f41, %f138, %f151;
	add.ftz.f32 	%f58, %f2, 0f00000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f47, %f48, %f49, %f50}, [texture1_RECT, {%f51, %f58}];
	// inline asm
	ld.shared.v4.f32 	{%f155, %f156, %f157, %f158}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+144];
	fma.rn.ftz.f32 	%f160, %f49, %f155, %f152;
	fma.rn.ftz.f32 	%f162, %f48, %f156, %f153;
	fma.rn.ftz.f32 	%f164, %f47, %f157, %f154;
	// inline asm
	tex.2d.v4.f32.f32 {%f53, %f54, %f55, %f56}, [texture1_RECT, {%f57, %f58}];
	// inline asm
	fma.rn.ftz.f32 	%f165, %f55, %f155, %f160;
	fma.rn.ftz.f32 	%f166, %f54, %f156, %f162;
	fma.rn.ftz.f32 	%f167, %f53, %f157, %f164;
	add.ftz.f32 	%f123, %f1, 0f00000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f59, %f60, %f61, %f62}, [texture1_RECT, {%f123, %f88}];
	// inline asm
	fma.rn.ftz.f32 	%f168, %f61, %f155, %f165;
	fma.rn.ftz.f32 	%f169, %f60, %f156, %f166;
	fma.rn.ftz.f32 	%f170, %f59, %f157, %f167;
	// inline asm
	tex.2d.v4.f32.f32 {%f65, %f66, %f67, %f68}, [texture1_RECT, {%f123, %f82}];
	// inline asm
	fma.rn.ftz.f32 	%f171, %f67, %f155, %f168;
	fma.rn.ftz.f32 	%f172, %f66, %f156, %f169;
	fma.rn.ftz.f32 	%f173, %f65, %f157, %f170;
	ld.shared.v4.f32 	{%f174, %f175, %f176, %f177}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+176];
	mul.ftz.f32 	%f179, %f171, %f174;
	mul.ftz.f32 	%f181, %f172, %f175;
	mul.ftz.f32 	%f183, %f173, %f176;
	setp.gt.ftz.f32	%p5, %f179, %f181;
	selp.f32	%f184, %f179, %f181, %p5;
	setp.gt.ftz.f32	%p6, %f184, %f183;
	selp.f32	%f185, %f184, %f183, %p6;
	cvt.ftz.sat.f32.f32	%f186, %f185;
	selp.f32	%f187, %f181, %f179, %p5;
	setp.gt.ftz.f32	%p7, %f187, %f183;
	selp.f32	%f188, %f183, %f187, %p7;
	cvt.ftz.sat.f32.f32	%f189, %f188;
	sub.ftz.f32 	%f190, %f186, %f189;
	setp.gt.ftz.f32	%p8, %f190, 0f2EDBE6FF;
	selp.f32	%f191, %f190, 0f2EDBE6FF, %p8;
	add.ftz.f32 	%f192, %f186, %f189;
	div.rn.ftz.f32 	%f193, %f135, %f191;
	div.rn.ftz.f32 	%f194, %f135, %f192;
	cvt.ftz.sat.f32.f32	%f195, %f179;
	cvt.ftz.sat.f32.f32	%f196, %f181;
	cvt.ftz.sat.f32.f32	%f197, %f183;
	sub.ftz.f32 	%f198, %f181, %f197;
	sub.ftz.f32 	%f199, %f183, %f195;
	sub.ftz.f32 	%f200, %f179, %f196;
	mul.ftz.f32 	%f201, %f193, %f198;
	mul.ftz.f32 	%f202, %f193, %f199;
	mul.ftz.f32 	%f203, %f193, %f200;
	fma.rn.ftz.f32 	%f204, %f201, 0f3E2AAAAB, 0f00000000;
	fma.rn.ftz.f32 	%f205, %f202, 0f3E2AAAAB, 0f3EAAAAAB;
	fma.rn.ftz.f32 	%f206, %f203, 0f3E2AAAAB, 0f3F2AAAAB;
	mov.f32 	%f207, 0f40000004;
	sub.ftz.f32 	%f208, %f207, %f192;
	div.rn.ftz.f32 	%f209, %f135, %f208;
	mul.ftz.f32 	%f210, %f192, 0f3F000000;
	mov.f32 	%f211, 0f3F000000;
	sub.ftz.f32 	%f212, %f211, %f210;
	setp.lt.ftz.f32	%p9, %f212, 0f00000000;
	selp.f32	%f213, %f209, %f194, %p9;
	mul.ftz.f32 	%f214, %f213, %f191;
	sub.ftz.f32 	%f215, %f179, %f186;
	sub.ftz.f32 	%f216, %f181, %f186;
	setp.lt.ftz.f32	%p10, %f215, 0f00000000;
	selp.f32	%f217, %f206, %f204, %p10;
	setp.lt.ftz.f32	%p11, %f216, 0f00000000;
	selp.f32	%f218, %f217, %f205, %p11;
	cvt.rmi.ftz.f32.f32	%f219, %f218;
	sub.ftz.f32 	%f220, %f218, %f219;
	ld.shared.v4.f32 	{%f221, %f222, %f223, %f224}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+80];
	sub.ftz.f32 	%f226, %f220, %f221;
	sub.ftz.f32 	%f228, %f210, %f222;
	sub.ftz.f32 	%f230, %f214, %f223;
	abs.ftz.f32 	%f231, %f226;
	abs.ftz.f32 	%f232, %f228;
	abs.ftz.f32 	%f233, %f230;
	add.ftz.f32 	%f234, %f231, 0fBF800000;
	abs.ftz.f32 	%f235, %f234;
	setp.gt.ftz.f32	%p12, %f235, %f231;
	selp.f32	%f236, %f231, %f235, %p12;
	ld.shared.v4.f32 	{%f237, %f238, %f239, %f240}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+96];
	sub.ftz.f32 	%f242, %f237, %f236;
	sub.ftz.f32 	%f244, %f238, %f232;
	sub.ftz.f32 	%f246, %f239, %f233;
	ld.shared.v4.f32 	{%f247, %f248, %f249, %f250}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+112];
	mul.ftz.f32 	%f252, %f242, %f247;
	cvt.ftz.sat.f32.f32	%f253, %f252;
	mul.ftz.f32 	%f255, %f244, %f248;
	cvt.ftz.sat.f32.f32	%f256, %f255;
	mul.ftz.f32 	%f258, %f246, %f249;
	cvt.ftz.sat.f32.f32	%f259, %f258;
	mul.ftz.f32 	%f260, %f253, %f256;
	mul.ftz.f32 	%f261, %f260, %f259;
	// inline asm
	tex.2d.v4.f32.f32 {%f71, %f72, %f73, %f74}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f77, %f78, %f79, %f80}, [texture0_RECT, {%f123, %f82}];
	// inline asm
	ld.shared.v4.f32 	{%f262, %f263, %f264, %f265}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local];
	fma.rn.ftz.f32 	%f267, %f79, %f262, %f73;
	fma.rn.ftz.f32 	%f269, %f78, %f263, %f72;
	fma.rn.ftz.f32 	%f271, %f77, %f264, %f71;
	fma.rn.ftz.f32 	%f273, %f80, %f265, %f74;
	// inline asm
	tex.2d.v4.f32.f32 {%f83, %f84, %f85, %f86}, [texture0_RECT, {%f123, %f88}];
	// inline asm
	fma.rn.ftz.f32 	%f274, %f85, %f262, %f267;
	fma.rn.ftz.f32 	%f275, %f84, %f263, %f269;
	fma.rn.ftz.f32 	%f276, %f83, %f264, %f271;
	fma.rn.ftz.f32 	%f277, %f86, %f265, %f273;
	add.ftz.f32 	%f94, %f2, 0fC0000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f89, %f90, %f91, %f92}, [texture0_RECT, {%f123, %f94}];
	// inline asm
	ld.shared.v4.f32 	{%f278, %f279, %f280, %f281}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+16];
	fma.rn.ftz.f32 	%f283, %f91, %f278, %f274;
	fma.rn.ftz.f32 	%f285, %f90, %f279, %f275;
	fma.rn.ftz.f32 	%f287, %f89, %f280, %f276;
	fma.rn.ftz.f32 	%f289, %f92, %f281, %f277;
	add.ftz.f32 	%f100, %f2, 0f40000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f95, %f96, %f97, %f98}, [texture0_RECT, {%f123, %f100}];
	// inline asm
	fma.rn.ftz.f32 	%f290, %f97, %f278, %f283;
	fma.rn.ftz.f32 	%f291, %f96, %f279, %f285;
	fma.rn.ftz.f32 	%f292, %f95, %f280, %f287;
	fma.rn.ftz.f32 	%f293, %f98, %f281, %f289;
	add.ftz.f32 	%f106, %f2, 0fC0400000;
	// inline asm
	tex.2d.v4.f32.f32 {%f101, %f102, %f103, %f104}, [texture0_RECT, {%f123, %f106}];
	// inline asm
	ld.shared.v4.f32 	{%f294, %f295, %f296, %f297}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+32];
	fma.rn.ftz.f32 	%f299, %f103, %f294, %f290;
	fma.rn.ftz.f32 	%f301, %f102, %f295, %f291;
	fma.rn.ftz.f32 	%f303, %f101, %f296, %f292;
	fma.rn.ftz.f32 	%f305, %f104, %f297, %f293;
	add.ftz.f32 	%f112, %f2, 0f40400000;
	// inline asm
	tex.2d.v4.f32.f32 {%f107, %f108, %f109, %f110}, [texture0_RECT, {%f123, %f112}];
	// inline asm
	fma.rn.ftz.f32 	%f306, %f109, %f294, %f299;
	fma.rn.ftz.f32 	%f307, %f108, %f295, %f301;
	fma.rn.ftz.f32 	%f308, %f107, %f296, %f303;
	fma.rn.ftz.f32 	%f309, %f110, %f297, %f305;
	add.ftz.f32 	%f118, %f2, 0fC0800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f113, %f114, %f115, %f116}, [texture0_RECT, {%f123, %f118}];
	// inline asm
	ld.shared.v4.f32 	{%f310, %f311, %f312, %f313}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+48];
	fma.rn.ftz.f32 	%f315, %f115, %f310, %f306;
	fma.rn.ftz.f32 	%f317, %f114, %f311, %f307;
	fma.rn.ftz.f32 	%f319, %f113, %f312, %f308;
	fma.rn.ftz.f32 	%f321, %f116, %f313, %f309;
	add.ftz.f32 	%f124, %f2, 0f40800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f119, %f120, %f121, %f122}, [texture0_RECT, {%f123, %f124}];
	// inline asm
	fma.rn.ftz.f32 	%f322, %f121, %f310, %f315;
	fma.rn.ftz.f32 	%f323, %f120, %f311, %f317;
	fma.rn.ftz.f32 	%f324, %f119, %f312, %f319;
	fma.rn.ftz.f32 	%f325, %f122, %f313, %f321;
	ld.shared.v4.f32 	{%f326, %f327, %f328, %f329}, [ShaderKernel_GaussianBlurRange$__cuda_local_var_180706_642_non_const_p_local+64];
	mul.ftz.f32 	%f331, %f322, %f326;
	mul.ftz.f32 	%f333, %f323, %f327;
	mul.ftz.f32 	%f335, %f324, %f328;
	mul.ftz.f32 	%f337, %f325, %f329;
	sub.ftz.f32 	%f338, %f135, %f261;
	mul.ftz.f32 	%f339, %f338, %f19;
	fma.rn.ftz.f32 	%f3, %f261, %f331, %f339;
	mul.ftz.f32 	%f340, %f338, %f18;
	fma.rn.ftz.f32 	%f4, %f261, %f333, %f340;
	mul.ftz.f32 	%f341, %f338, %f17;
	fma.rn.ftz.f32 	%f5, %f261, %f335, %f341;
	mul.ftz.f32 	%f342, %f338, %f20;
	fma.rn.ftz.f32 	%f6, %f261, %f337, %f342;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p13, %r5, 0;
	@%p13 bra 	BB0_5;

	shl.b64 	%rd46, %rd2, 4;
	add.s64 	%rd47, %rd1, %rd46;
	st.global.v4.f32 	[%rd47], {%f5, %f4, %f3, %f6};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd48, %rd2, 3;
	add.s64 	%rd49, %rd1, %rd48;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f6;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd49], {%rs4, %rs3, %rs2, %rs1};

BB0_6:
	ret;
}


