//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local has been demoted

.visible .entry ShaderKernel_fxTinting(
	.param .u64 ShaderKernel_fxTinting_param_0,
	.param .u32 ShaderKernel_fxTinting_param_1,
	.param .u32 ShaderKernel_fxTinting_param_2,
	.param .u32 ShaderKernel_fxTinting_param_3,
	.param .u32 ShaderKernel_fxTinting_param_4,
	.param .u64 ShaderKernel_fxTinting_param_5,
	.param .u64 ShaderKernel_fxTinting_param_6
)
{
	.reg .pred 	%p<30>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<124>;
	.reg .s64 	%rd<15>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local[112];

	ld.param.u64 	%rd4, [ShaderKernel_fxTinting_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxTinting_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxTinting_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxTinting_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxTinting_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_fxTinting_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 6;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd5, %rd6;
	ld.global.v4.f32 	{%f7, %f8, %f9, %f10}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f7, %f8, %f9, %f10};

BB0_3:
	cvt.rn.f32.s32	%f15, %r2;
	add.ftz.f32 	%f1, %f15, 0f3F000000;
	cvt.rn.f32.s32	%f16, %r3;
	add.ftz.f32 	%f2, %f16, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	mov.f32 	%f23, 0f3F800000;
	sub.ftz.f32 	%f24, %f23, %f19;
	sub.ftz.f32 	%f25, %f23, %f18;
	sub.ftz.f32 	%f26, %f23, %f17;
	sub.ftz.f32 	%f27, %f23, %f20;
	ld.shared.v4.f32 	{%f28, %f29, %f30, %f31}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local+16];
	mul.ftz.f32 	%f33, %f24, %f28;
	mul.ftz.f32 	%f35, %f25, %f29;
	mul.ftz.f32 	%f37, %f26, %f30;
	mul.ftz.f32 	%f39, %f27, %f31;
	ld.shared.v4.f32 	{%f40, %f41, %f42, %f43}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local];
	mul.ftz.f32 	%f45, %f19, %f40;
	mul.ftz.f32 	%f47, %f18, %f41;
	mul.ftz.f32 	%f49, %f17, %f42;
	mul.ftz.f32 	%f51, %f20, %f43;
	add.ftz.f32 	%f52, %f19, %f40;
	add.ftz.f32 	%f53, %f18, %f41;
	add.ftz.f32 	%f54, %f17, %f42;
	add.ftz.f32 	%f55, %f20, %f43;
	sub.ftz.f32 	%f56, %f23, %f33;
	sub.ftz.f32 	%f57, %f23, %f35;
	sub.ftz.f32 	%f58, %f23, %f37;
	sub.ftz.f32 	%f59, %f23, %f39;
	setp.gt.ftz.f32	%p5, %f19, %f40;
	selp.f32	%f60, %f19, %f40, %p5;
	setp.gt.ftz.f32	%p6, %f18, %f41;
	selp.f32	%f61, %f18, %f41, %p6;
	setp.gt.ftz.f32	%p7, %f17, %f42;
	selp.f32	%f62, %f17, %f42, %p7;
	setp.gt.ftz.f32	%p8, %f20, %f43;
	selp.f32	%f63, %f20, %f43, %p8;
	selp.f32	%f64, %f40, %f19, %p5;
	selp.f32	%f65, %f41, %f18, %p6;
	selp.f32	%f66, %f42, %f17, %p7;
	selp.f32	%f67, %f43, %f20, %p8;
	ld.shared.v4.f32 	{%f68, %f69, %f70, %f71}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local+32];
	setp.lt.ftz.f32	%p9, %f68, 0f00000000;
	selp.f32	%f73, %f40, %f45, %p9;
	setp.lt.ftz.f32	%p10, %f69, 0f00000000;
	selp.f32	%f75, %f41, %f47, %p10;
	setp.lt.ftz.f32	%p11, %f70, 0f00000000;
	selp.f32	%f77, %f42, %f49, %p11;
	setp.lt.ftz.f32	%p12, %f71, 0f00000000;
	selp.f32	%f79, %f43, %f51, %p12;
	ld.shared.v4.f32 	{%f80, %f81, %f82, %f83}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local+48];
	setp.lt.ftz.f32	%p13, %f80, 0f00000000;
	selp.f32	%f85, %f73, %f52, %p13;
	setp.lt.ftz.f32	%p14, %f81, 0f00000000;
	selp.f32	%f87, %f75, %f53, %p14;
	setp.lt.ftz.f32	%p15, %f82, 0f00000000;
	selp.f32	%f89, %f77, %f54, %p15;
	setp.lt.ftz.f32	%p16, %f83, 0f00000000;
	selp.f32	%f91, %f79, %f55, %p16;
	ld.shared.v4.f32 	{%f92, %f93, %f94, %f95}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local+64];
	setp.lt.ftz.f32	%p17, %f92, 0f00000000;
	selp.f32	%f97, %f85, %f56, %p17;
	setp.lt.ftz.f32	%p18, %f93, 0f00000000;
	selp.f32	%f99, %f87, %f57, %p18;
	setp.lt.ftz.f32	%p19, %f94, 0f00000000;
	selp.f32	%f101, %f89, %f58, %p19;
	setp.lt.ftz.f32	%p20, %f95, 0f00000000;
	selp.f32	%f103, %f91, %f59, %p20;
	ld.shared.v4.f32 	{%f104, %f105, %f106, %f107}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local+80];
	setp.lt.ftz.f32	%p21, %f104, 0f00000000;
	selp.f32	%f109, %f97, %f60, %p21;
	setp.lt.ftz.f32	%p22, %f105, 0f00000000;
	selp.f32	%f111, %f99, %f61, %p22;
	setp.lt.ftz.f32	%p23, %f106, 0f00000000;
	selp.f32	%f113, %f101, %f62, %p23;
	setp.lt.ftz.f32	%p24, %f107, 0f00000000;
	selp.f32	%f115, %f103, %f63, %p24;
	ld.shared.v4.f32 	{%f116, %f117, %f118, %f119}, [ShaderKernel_fxTinting$__cuda_local_var_180679_469_non_const_p_local+96];
	setp.lt.ftz.f32	%p25, %f116, 0f00000000;
	selp.f32	%f3, %f109, %f64, %p25;
	setp.lt.ftz.f32	%p26, %f117, 0f00000000;
	selp.f32	%f4, %f111, %f65, %p26;
	setp.lt.ftz.f32	%p27, %f118, 0f00000000;
	selp.f32	%f5, %f113, %f66, %p27;
	setp.lt.ftz.f32	%p28, %f119, 0f00000000;
	selp.f32	%f6, %f115, %f67, %p28;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p29, %r5, 0;
	@%p29 bra 	BB0_5;

	shl.b64 	%rd11, %rd2, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f5, %f4, %f3, %f6};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd13, %rd2, 3;
	add.s64 	%rd14, %rd1, %rd13;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f6;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs4, %rs3, %rs2, %rs1};

BB0_6:
	ret;
}


