//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
.global .texref texture2_3D;

.visible .entry ShaderKernel_fxTechnicolor3strip(
	.param .u64 ShaderKernel_fxTechnicolor3strip_param_0,
	.param .u32 ShaderKernel_fxTechnicolor3strip_param_1,
	.param .u32 ShaderKernel_fxTechnicolor3strip_param_2,
	.param .u32 ShaderKernel_fxTechnicolor3strip_param_3,
	.param .u32 ShaderKernel_fxTechnicolor3strip_param_4,
	.param .u64 ShaderKernel_fxTechnicolor3strip_param_5,
	.param .u64 ShaderKernel_fxTechnicolor3strip_param_6,
	.param .u64 ShaderKernel_fxTechnicolor3strip_param_7
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<24>;
	.reg .s64 	%rd<12>;


	ld.param.u64 	%rd3, [ShaderKernel_fxTechnicolor3strip_param_0];
	ld.param.u32 	%r3, [ShaderKernel_fxTechnicolor3strip_param_1];
	ld.param.u32 	%r4, [ShaderKernel_fxTechnicolor3strip_param_2];
	ld.param.u32 	%r5, [ShaderKernel_fxTechnicolor3strip_param_3];
	ld.param.u32 	%r6, [ShaderKernel_fxTechnicolor3strip_param_4];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f19, %r1;
	add.ftz.f32 	%f9, %f19, 0f3F000000;
	cvt.rn.f32.s32	%f20, %r2;
	add.ftz.f32 	%f10, %f20, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f5, %f6, %f7, %f8}, [texture0_RECT, {%f9, %f10}];
	// inline asm
	cvt.ftz.sat.f32.f32	%f21, %f7;
	cvt.ftz.sat.f32.f32	%f22, %f6;
	cvt.ftz.sat.f32.f32	%f23, %f5;
	fma.rn.ftz.f32 	%f15, %f21, 0f3F400000, 0f3C800000;
	fma.rn.ftz.f32 	%f16, %f22, 0f3F400000, 0f3C800000;
	fma.rn.ftz.f32 	%f17, %f23, 0f3F400000, 0f3C800000;
	mov.f32 	%f18, 0f00000000;
	// inline asm
	tex.3d.v4.f32.f32 {%f11, %f12, %f13, %f14}, [texture2_3D, {%f15, %f16, %f17, %f18}];
	// inline asm
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p4, %r4, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd8, %rd2, 4;
	add.s64 	%rd9, %rd1, %rd8;
	st.global.v4.f32 	[%rd9], {%f13, %f12, %f11, %f8};
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd10, %rd2, 3;
	add.s64 	%rd11, %rd1, %rd10;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f8;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f11;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f12;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f13;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd11], {%rs4, %rs3, %rs2, %rs1};

BB0_4:
	ret;
}


