//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;

.visible .entry ShaderKernel_fxSobelOperator(
	.param .u64 ShaderKernel_fxSobelOperator_param_0,
	.param .u32 ShaderKernel_fxSobelOperator_param_1,
	.param .u32 ShaderKernel_fxSobelOperator_param_2,
	.param .u32 ShaderKernel_fxSobelOperator_param_3,
	.param .u32 ShaderKernel_fxSobelOperator_param_4,
	.param .u64 ShaderKernel_fxSobelOperator_param_5,
	.param .u64 ShaderKernel_fxSobelOperator_param_6
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<98>;
	.reg .s64 	%rd<26>;


	ld.param.u64 	%rd3, [ShaderKernel_fxSobelOperator_param_0];
	ld.param.u32 	%r3, [ShaderKernel_fxSobelOperator_param_1];
	ld.param.u32 	%r4, [ShaderKernel_fxSobelOperator_param_2];
	ld.param.u32 	%r5, [ShaderKernel_fxSobelOperator_param_3];
	ld.param.u32 	%r6, [ShaderKernel_fxSobelOperator_param_4];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f59, %r1;
	add.ftz.f32 	%f57, %f59, 0f3F000000;
	cvt.rn.f32.s32	%f60, %r2;
	add.ftz.f32 	%f58, %f60, 0f3F000000;
	add.ftz.f32 	%f39, %f57, 0f00000000;
	add.ftz.f32 	%f28, %f58, 0fBF800000;
	add.ftz.f32 	%f33, %f57, 0fBF800000;
	add.ftz.f32 	%f52, %f58, 0f00000000;
	add.ftz.f32 	%f46, %f58, 0f3F800000;
	mov.f32 	%f61, 0f3F800000;
	add.ftz.f32 	%f51, %f57, 0f3F800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f5, %f6, %f7, %f8}, [texture0_RECT, {%f33, %f46}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f11, %f12, %f13, %f14}, [texture0_RECT, {%f51, %f28}];
	// inline asm
	sub.ftz.f32 	%f62, %f13, %f7;
	sub.ftz.f32 	%f63, %f12, %f6;
	sub.ftz.f32 	%f64, %f11, %f5;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [texture0_RECT, {%f33, %f28}];
	// inline asm
	sub.ftz.f32 	%f65, %f62, %f19;
	sub.ftz.f32 	%f66, %f63, %f18;
	sub.ftz.f32 	%f67, %f64, %f17;
	add.ftz.f32 	%f68, %f19, %f62;
	add.ftz.f32 	%f69, %f18, %f63;
	add.ftz.f32 	%f70, %f17, %f64;
	// inline asm
	tex.2d.v4.f32.f32 {%f23, %f24, %f25, %f26}, [texture0_RECT, {%f39, %f28}];
	// inline asm
	fma.rn.ftz.f32 	%f71, %f25, 0f40000000, %f68;
	fma.rn.ftz.f32 	%f72, %f24, 0f40000000, %f69;
	fma.rn.ftz.f32 	%f73, %f23, 0f40000000, %f70;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [texture0_RECT, {%f33, %f52}];
	// inline asm
	fma.rn.ftz.f32 	%f74, %f31, 0fC0000000, %f65;
	fma.rn.ftz.f32 	%f75, %f30, 0fC0000000, %f66;
	fma.rn.ftz.f32 	%f76, %f29, 0fC0000000, %f67;
	// inline asm
	tex.2d.v4.f32.f32 {%f35, %f36, %f37, %f38}, [texture0_RECT, {%f39, %f46}];
	// inline asm
	fma.rn.ftz.f32 	%f77, %f37, 0fC0000000, %f71;
	fma.rn.ftz.f32 	%f78, %f36, 0fC0000000, %f72;
	fma.rn.ftz.f32 	%f79, %f35, 0fC0000000, %f73;
	// inline asm
	tex.2d.v4.f32.f32 {%f41, %f42, %f43, %f44}, [texture0_RECT, {%f51, %f46}];
	// inline asm
	add.ftz.f32 	%f80, %f43, %f74;
	add.ftz.f32 	%f81, %f42, %f75;
	add.ftz.f32 	%f82, %f41, %f76;
	sub.ftz.f32 	%f83, %f77, %f43;
	sub.ftz.f32 	%f84, %f78, %f42;
	sub.ftz.f32 	%f85, %f79, %f41;
	// inline asm
	tex.2d.v4.f32.f32 {%f47, %f48, %f49, %f50}, [texture0_RECT, {%f51, %f52}];
	// inline asm
	fma.rn.ftz.f32 	%f86, %f49, 0f40000000, %f80;
	fma.rn.ftz.f32 	%f87, %f48, 0f40000000, %f81;
	fma.rn.ftz.f32 	%f88, %f47, 0f40000000, %f82;
	mul.ftz.f32 	%f89, %f86, %f86;
	mul.ftz.f32 	%f90, %f87, %f87;
	mul.ftz.f32 	%f91, %f88, %f88;
	fma.rn.ftz.f32 	%f92, %f83, %f83, %f89;
	fma.rn.ftz.f32 	%f93, %f84, %f84, %f90;
	fma.rn.ftz.f32 	%f94, %f85, %f85, %f91;
	rsqrt.approx.ftz.f32 	%f95, %f92;
	div.rn.ftz.f32 	%f1, %f61, %f95;
	rsqrt.approx.ftz.f32 	%f96, %f93;
	div.rn.ftz.f32 	%f2, %f61, %f96;
	rsqrt.approx.ftz.f32 	%f97, %f94;
	div.rn.ftz.f32 	%f3, %f61, %f97;
	// inline asm
	tex.2d.v4.f32.f32 {%f53, %f54, %f55, %f56}, [texture0_RECT, {%f57, %f58}];
	// inline asm
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p4, %r4, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd22, %rd2, 4;
	add.s64 	%rd23, %rd1, %rd22;
	st.global.v4.f32 	[%rd23], {%f3, %f2, %f1, %f56};
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd24, %rd2, 3;
	add.s64 	%rd25, %rd1, %rd24;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f56;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f1;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f2;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd25], {%rs4, %rs3, %rs2, %rs1};

BB0_4:
	ret;
}


