//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_fxLegalizeNTSC$__cuda_local_var_180673_474_non_const_p_local has been demoted

.visible .entry ShaderKernel_fxLegalizeNTSC(
	.param .u64 ShaderKernel_fxLegalizeNTSC_param_0,
	.param .u32 ShaderKernel_fxLegalizeNTSC_param_1,
	.param .u32 ShaderKernel_fxLegalizeNTSC_param_2,
	.param .u32 ShaderKernel_fxLegalizeNTSC_param_3,
	.param .u32 ShaderKernel_fxLegalizeNTSC_param_4,
	.param .u64 ShaderKernel_fxLegalizeNTSC_param_5,
	.param .u64 ShaderKernel_fxLegalizeNTSC_param_6
)
{
	.reg .pred 	%p<13>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<82>;
	.reg .s64 	%rd<11>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxLegalizeNTSC$__cuda_local_var_180673_474_non_const_p_local[16];

	ld.param.u64 	%rd4, [ShaderKernel_fxLegalizeNTSC_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxLegalizeNTSC_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxLegalizeNTSC_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxLegalizeNTSC_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxLegalizeNTSC_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_fxLegalizeNTSC_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	ld.global.v4.f32 	{%f7, %f8, %f9, %f10}, [%rd5];
	st.shared.v4.f32 	[ShaderKernel_fxLegalizeNTSC$__cuda_local_var_180673_474_non_const_p_local], {%f7, %f8, %f9, %f10};

BB0_3:
	cvt.rn.f32.s32	%f15, %r2;
	add.ftz.f32 	%f1, %f15, 0f3F000000;
	cvt.rn.f32.s32	%f16, %r3;
	add.ftz.f32 	%f2, %f16, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f17, %f18, %f19, %f20}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	cvt.ftz.sat.f32.f32	%f23, %f19;
	cvt.ftz.sat.f32.f32	%f24, %f18;
	cvt.ftz.sat.f32.f32	%f25, %f17;
	mul.ftz.f32 	%f26, %f24, 0f3F162B6B;
	fma.rn.ftz.f32 	%f27, %f23, 0f3E99096C, %f26;
	fma.rn.ftz.f32 	%f28, %f25, 0f3DEA4A8C, %f27;
	mul.ftz.f32 	%f29, %f24, 0fBE8C56D6;
	fma.rn.ftz.f32 	%f30, %f23, 0f3F188CE7, %f29;
	fma.rn.ftz.f32 	%f31, %f25, 0fBEA4C2F8, %f30;
	mul.ftz.f32 	%f32, %f24, 0fBF05CFAB;
	fma.rn.ftz.f32 	%f33, %f23, 0f3E585F07, %f32;
	fma.rn.ftz.f32 	%f34, %f25, 0f3E9F62B7, %f33;
	mul.ftz.f32 	%f35, %f34, %f34;
	fma.rn.ftz.f32 	%f36, %f31, %f31, %f35;
	add.ftz.f32 	%f37, %f36, 0f00000000;
	rsqrt.approx.ftz.f32 	%f38, %f37;
	mul.ftz.f32 	%f39, %f37, %f38;
	add.ftz.f32 	%f40, %f39, %f28;
	fma.rn.ftz.f32 	%f41, %f39, 0fBF800000, %f28;
	fma.rn.ftz.f32 	%f42, %f39, 0f3FA185F0, 0f00000000;
	fma.rn.ftz.f32 	%f43, %f40, 0f3F0ED23A, 0f00000000;
	fma.rn.ftz.f32 	%f44, %f41, 0fBF0ED23A, 0f3F0ED23A;
	ld.shared.v4.f32 	{%f45, %f46, %f47, %f48}, [ShaderKernel_fxLegalizeNTSC$__cuda_local_var_180673_474_non_const_p_local];
	mul.ftz.f32 	%f50, %f43, %f46;
	fma.rn.ftz.f32 	%f52, %f42, %f45, %f50;
	fma.rn.ftz.f32 	%f54, %f44, %f47, %f52;
	add.ftz.f32 	%f56, %f54, %f48;
	cvt.ftz.sat.f32.f32	%f57, %f56;
	mul.ftz.f32 	%f58, %f39, %f57;
	sub.ftz.f32 	%f59, %f39, %f58;
	add.ftz.f32 	%f60, %f59, %f28;
	fma.rn.ftz.f32 	%f61, %f59, 0fBF800000, %f28;
	setp.gt.ftz.f32	%p5, %f61, 0fBE981062;
	selp.f32	%f62, %f61, 0fBE981062, %p5;
	setp.gt.ftz.f32	%p6, %f60, 0f3F7FBE77;
	selp.f32	%f63, 0f3F7FBE77, %f60, %p6;
	sub.ftz.f32 	%f64, %f63, %f28;
	sub.ftz.f32 	%f65, %f28, %f62;
	setp.gt.ftz.f32	%p7, %f65, %f64;
	selp.f32	%f66, %f64, %f65, %p7;
	setp.gt.ftz.f32	%p8, %f66, 0f3F09BA5E;
	selp.f32	%f67, 0f3F09BA5E, %f66, %p8;
	mov.f32 	%f68, 0f3F800000;
	div.rn.ftz.f32 	%f69, %f68, %f39;
	mul.ftz.f32 	%f70, %f69, %f67;
	mul.ftz.f32 	%f71, %f70, %f31;
	mul.ftz.f32 	%f72, %f70, %f34;
	mul.ftz.f32 	%f73, %f71, 0f3F74CDFD;
	fma.rn.ftz.f32 	%f74, %f28, 0f3F800550, %f73;
	fma.rn.ftz.f32 	%f75, %f72, 0f3F1EF803, %f74;
	mul.ftz.f32 	%f76, %f71, 0fBE8B1CF2;
	fma.rn.ftz.f32 	%f77, %f28, 0f3F800127, %f76;
	fma.rn.ftz.f32 	%f78, %f72, 0fBF25FBD3, %f77;
	mul.ftz.f32 	%f79, %f71, 0fBF8D7A75;
	fma.rn.ftz.f32 	%f80, %f28, 0f3F8008DB, %f79;
	fma.rn.ftz.f32 	%f81, %f72, 0f3FD9E083, %f80;
	setp.gt.ftz.f32	%p9, %f75, 0f00000000;
	selp.f32	%f3, %f75, 0f00000000, %p9;
	setp.gt.ftz.f32	%p10, %f78, 0f00000000;
	selp.f32	%f4, %f78, 0f00000000, %p10;
	setp.gt.ftz.f32	%p11, %f81, 0f00000000;
	selp.f32	%f5, %f81, 0f00000000, %p11;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p12, %r5, 0;
	@%p12 bra 	BB0_5;

	shl.b64 	%rd7, %rd2, 4;
	add.s64 	%rd8, %rd1, %rd7;
	st.global.v4.f32 	[%rd8], {%f5, %f4, %f3, %f20};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd9, %rd2, 3;
	add.s64 	%rd10, %rd1, %rd9;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f5;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd10], {%rs4, %rs3, %rs2, %rs1};

BB0_6:
	ret;
}


