//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_fxEmboss$__cuda_local_var_180673_468_non_const_p_local has been demoted

.visible .entry ShaderKernel_fxEmboss(
	.param .u64 ShaderKernel_fxEmboss_param_0,
	.param .u32 ShaderKernel_fxEmboss_param_1,
	.param .u32 ShaderKernel_fxEmboss_param_2,
	.param .u32 ShaderKernel_fxEmboss_param_3,
	.param .u32 ShaderKernel_fxEmboss_param_4,
	.param .u64 ShaderKernel_fxEmboss_param_5,
	.param .u64 ShaderKernel_fxEmboss_param_6
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<3>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<52>;
	.reg .s64 	%rd<16>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxEmboss$__cuda_local_var_180673_468_non_const_p_local[16];

	ld.param.u64 	%rd4, [ShaderKernel_fxEmboss_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxEmboss_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxEmboss_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxEmboss_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxEmboss_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_fxEmboss_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_6;
	bra.uni 	BB0_1;

BB0_1:
	setp.ne.s32	%p4, %r1, 0;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	ld.global.v4.f32 	{%f5, %f6, %f7, %f8}, [%rd5];
	st.shared.v4.f32 	[ShaderKernel_fxEmboss$__cuda_local_var_180673_468_non_const_p_local], {%f5, %f6, %f7, %f8};

BB0_3:
	cvt.rn.f32.s32	%f13, %r2;
	add.ftz.f32 	%f1, %f13, 0f3F000000;
	cvt.rn.f32.s32	%f14, %r3;
	add.ftz.f32 	%f2, %f14, 0f3F000000;
	bar.sync 	0;
	// inline asm
	tex.2d.v4.f32.f32 {%f15, %f16, %f17, %f18}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	mul.ftz.f32 	%f33, %f17, 0fC0400000;
	mul.ftz.f32 	%f34, %f16, 0fC0400000;
	mul.ftz.f32 	%f35, %f15, 0fC0400000;
	add.ftz.f32 	%f26, %f2, 0fBF800000;
	add.ftz.f32 	%f25, %f1, 0f00000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f25, %f26}];
	// inline asm
	fma.rn.ftz.f32 	%f36, %f23, 0f3FC00000, %f33;
	fma.rn.ftz.f32 	%f37, %f22, 0f3FC00000, %f34;
	fma.rn.ftz.f32 	%f38, %f21, 0f3FC00000, %f35;
	add.ftz.f32 	%f32, %f2, 0f00000000;
	add.ftz.f32 	%f31, %f1, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f27, %f28, %f29, %f30}, [texture0_RECT, {%f31, %f32}];
	// inline asm
	fma.rn.ftz.f32 	%f39, %f29, 0f3FC00000, %f36;
	fma.rn.ftz.f32 	%f40, %f28, 0f3FC00000, %f37;
	fma.rn.ftz.f32 	%f41, %f27, 0f3FC00000, %f38;
	ld.shared.v4.f32 	{%f42, %f43, %f44, %f45}, [ShaderKernel_fxEmboss$__cuda_local_var_180673_468_non_const_p_local];
	mul.ftz.f32 	%f47, %f40, %f43;
	fma.rn.ftz.f32 	%f49, %f39, %f42, %f47;
	fma.rn.ftz.f32 	%f51, %f41, %f44, %f49;
	add.ftz.f32 	%f4, %f51, 0f3EAAAAAB;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p5, %r5, 0;
	@%p5 bra 	BB0_5;

	shl.b64 	%rd12, %rd2, 4;
	add.s64 	%rd13, %rd1, %rd12;
	st.global.v4.f32 	[%rd13], {%f4, %f4, %f4, %f18};
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd14, %rd2, 3;
	add.s64 	%rd15, %rd1, %rd14;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f18;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs2, %temp;
}
	st.global.v4.u16 	[%rd15], {%rs2, %rs2, %rs2, %rs1};

BB0_6:
	ret;
}


