//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;
// ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local has been demoted

.visible .entry ShaderKernel_fxCopperplate(
	.param .u64 ShaderKernel_fxCopperplate_param_0,
	.param .u32 ShaderKernel_fxCopperplate_param_1,
	.param .u32 ShaderKernel_fxCopperplate_param_2,
	.param .u32 ShaderKernel_fxCopperplate_param_3,
	.param .u32 ShaderKernel_fxCopperplate_param_4,
	.param .u64 ShaderKernel_fxCopperplate_param_5,
	.param .u64 ShaderKernel_fxCopperplate_param_6
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<130>;
	.reg .s64 	%rd<24>;
	// demoted variable
	.shared .align 16 .b8 ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local[80];

	ld.param.u64 	%rd4, [ShaderKernel_fxCopperplate_param_0];
	ld.param.u32 	%r4, [ShaderKernel_fxCopperplate_param_1];
	ld.param.u32 	%r5, [ShaderKernel_fxCopperplate_param_2];
	ld.param.u32 	%r6, [ShaderKernel_fxCopperplate_param_3];
	ld.param.u32 	%r7, [ShaderKernel_fxCopperplate_param_4];
	ld.param.u64 	%rd3, [ShaderKernel_fxCopperplate_param_5];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r1, %tid.x;
	mad.lo.s32 	%r2, %r8, %r9, %r1;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r3, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r2, %r6;
	setp.lt.s32	%p2, %r3, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_9;
	bra.uni 	BB0_1;

BB0_1:
	setp.gt.u32	%p4, %r1, 4;
	@%p4 bra 	BB0_3;

	cvta.to.global.u64 	%rd5, %rd3;
	mul.wide.u32 	%rd6, %r1, 16;
	mov.u64 	%rd7, ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local;
	add.s64 	%rd8, %rd7, %rd6;
	add.s64 	%rd9, %rd5, %rd6;
	ld.global.v4.f32 	{%f11, %f12, %f13, %f14}, [%rd9];
	st.shared.v4.f32 	[%rd8], {%f11, %f12, %f13, %f14};

BB0_3:
	cvt.rn.f32.s32	%f19, %r2;
	add.ftz.f32 	%f1, %f19, 0f3F000000;
	cvt.rn.f32.s32	%f20, %r3;
	add.ftz.f32 	%f2, %f20, 0f3F000000;
	bar.sync 	0;
	add.ftz.f32 	%f32, %f2, 0f00000000;
	add.ftz.f32 	%f25, %f1, 0f3F800000;
	mov.f32 	%f51, 0f3F800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f21, %f22, %f23, %f24}, [texture0_RECT, {%f25, %f32}];
	// inline asm
	ld.shared.v4.f32 	{%f52, %f53, %f54, %f55}, [ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local+64];
	mul.ftz.f32 	%f57, %f22, %f53;
	fma.rn.ftz.f32 	%f59, %f23, %f52, %f57;
	fma.rn.ftz.f32 	%f61, %f21, %f54, %f59;
	add.ftz.f32 	%f31, %f1, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f27, %f28, %f29, %f30}, [texture0_RECT, {%f31, %f32}];
	// inline asm
	mul.ftz.f32 	%f62, %f28, %f53;
	fma.rn.ftz.f32 	%f63, %f29, %f52, %f62;
	fma.rn.ftz.f32 	%f64, %f27, %f54, %f63;
	sub.ftz.f32 	%f65, %f61, %f64;
	add.ftz.f32 	%f38, %f2, 0f3F800000;
	add.ftz.f32 	%f43, %f1, 0f00000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f33, %f34, %f35, %f36}, [texture0_RECT, {%f43, %f38}];
	// inline asm
	mul.ftz.f32 	%f66, %f34, %f53;
	fma.rn.ftz.f32 	%f67, %f35, %f52, %f66;
	fma.rn.ftz.f32 	%f68, %f33, %f54, %f67;
	add.ftz.f32 	%f44, %f2, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f39, %f40, %f41, %f42}, [texture0_RECT, {%f43, %f44}];
	// inline asm
	mul.ftz.f32 	%f69, %f40, %f53;
	fma.rn.ftz.f32 	%f70, %f41, %f52, %f69;
	fma.rn.ftz.f32 	%f71, %f39, %f54, %f70;
	sub.ftz.f32 	%f72, %f68, %f71;
	mul.ftz.f32 	%f73, %f72, 0f00000000;
	sub.ftz.f32 	%f74, %f73, %f65;
	mul.ftz.f32 	%f75, %f65, 0f00000000;
	mul.ftz.f32 	%f76, %f72, 0f3F800000;
	sub.ftz.f32 	%f77, %f75, %f76;
	mul.ftz.f32 	%f78, %f77, %f77;
	fma.rn.ftz.f32 	%f79, %f74, %f74, %f78;
	sub.ftz.f32 	%f80, %f51, 0f00000000;
	fma.rn.ftz.f32 	%f81, %f80, %f80, %f79;
	rsqrt.approx.ftz.f32 	%f82, %f81;
	mul.ftz.f32 	%f83, %f74, %f82;
	mul.ftz.f32 	%f84, %f77, %f82;
	mul.ftz.f32 	%f85, %f80, %f82;
	// inline asm
	tex.2d.v4.f32.f32 {%f45, %f46, %f47, %f48}, [texture0_RECT, {%f1, %f2}];
	// inline asm
	mul.ftz.f32 	%f86, %f46, %f53;
	fma.rn.ftz.f32 	%f87, %f47, %f52, %f86;
	fma.rn.ftz.f32 	%f4, %f45, %f54, %f87;
	mul.ftz.f32 	%f88, %f84, 0f00000000;
	fma.rn.ftz.f32 	%f89, %f83, 0f00000000, %f88;
	add.ftz.f32 	%f90, %f89, %f85;
	add.ftz.f32 	%f91, %f90, %f90;
	fma.rn.ftz.f32 	%f92, %f91, %f83, 0f80000000;
	fma.rn.ftz.f32 	%f93, %f91, %f84, 0f80000000;
	fma.rn.ftz.f32 	%f94, %f91, %f85, 0fBF800000;
	mul.ftz.f32 	%f95, %f93, 0f3E895E9E;
	fma.rn.ftz.f32 	%f96, %f92, 0f3EB72DA1, %f95;
	fma.rn.ftz.f32 	%f97, %f94, 0f3F64F766, %f96;
	cvt.ftz.sat.f32.f32	%f5, %f97;
	setp.gtu.ftz.f32	%p5, %f5, 0f00000000;
	@%p5 bra 	BB0_5;

	mov.f32 	%f129, 0f00000000;
	bra.uni 	BB0_6;

BB0_5:
	ld.shared.f32 	%f99, [ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local];
	lg2.approx.ftz.f32 	%f100, %f5;
	mul.ftz.f32 	%f101, %f100, %f99;
	ex2.approx.ftz.f32 	%f129, %f101;

BB0_6:
	ld.shared.v4.f32 	{%f102, %f103, %f104, %f105}, [ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local+32];
	mul.ftz.f32 	%f107, %f102, %f4;
	mul.ftz.f32 	%f109, %f103, %f4;
	mul.ftz.f32 	%f111, %f104, %f4;
	ld.shared.v4.f32 	{%f112, %f113, %f114, %f115}, [ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local+16];
	fma.rn.ftz.f32 	%f117, %f107, %f112, %f107;
	fma.rn.ftz.f32 	%f119, %f109, %f113, %f109;
	fma.rn.ftz.f32 	%f121, %f111, %f114, %f111;
	ld.shared.v4.f32 	{%f122, %f123, %f124, %f125}, [ShaderKernel_fxCopperplate$__cuda_local_var_180677_473_non_const_p_local+48];
	fma.rn.ftz.f32 	%f8, %f129, %f122, %f117;
	fma.rn.ftz.f32 	%f9, %f129, %f123, %f119;
	fma.rn.ftz.f32 	%f10, %f129, %f124, %f121;
	mad.lo.s32 	%r13, %r3, %r4, %r2;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p6, %r5, 0;
	@%p6 bra 	BB0_8;

	shl.b64 	%rd20, %rd2, 4;
	add.s64 	%rd21, %rd1, %rd20;
	st.global.v4.f32 	[%rd21], {%f10, %f9, %f8, %f48};
	bra.uni 	BB0_9;

BB0_8:
	shl.b64 	%rd22, %rd2, 3;
	add.s64 	%rd23, %rd1, %rd22;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f48;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f8;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f9;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f10;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd23], {%rs4, %rs3, %rs2, %rs1};

BB0_9:
	ret;
}


