//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref texture0_RECT;

.visible .entry ShaderKernel_fxAntiAliasH(
	.param .u64 ShaderKernel_fxAntiAliasH_param_0,
	.param .u32 ShaderKernel_fxAntiAliasH_param_1,
	.param .u32 ShaderKernel_fxAntiAliasH_param_2,
	.param .u32 ShaderKernel_fxAntiAliasH_param_3,
	.param .u32 ShaderKernel_fxAntiAliasH_param_4,
	.param .u64 ShaderKernel_fxAntiAliasH_param_5,
	.param .u64 ShaderKernel_fxAntiAliasH_param_6
)
{
	.reg .pred 	%p<10>;
	.reg .s16 	%rs<2>;
	.reg .s32 	%r<14>;
	.reg .f32 	%f<154>;
	.reg .s64 	%rd<26>;


	ld.param.u64 	%rd3, [ShaderKernel_fxAntiAliasH_param_0];
	ld.param.u32 	%r3, [ShaderKernel_fxAntiAliasH_param_1];
	ld.param.u32 	%r4, [ShaderKernel_fxAntiAliasH_param_2];
	ld.param.u32 	%r5, [ShaderKernel_fxAntiAliasH_param_3];
	ld.param.u32 	%r6, [ShaderKernel_fxAntiAliasH_param_4];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r7, %ntid.x;
	mov.u32 	%r8, %ctaid.x;
	mov.u32 	%r9, %tid.x;
	mad.lo.s32 	%r1, %r7, %r8, %r9;
	mov.u32 	%r10, %ntid.y;
	mov.u32 	%r11, %ctaid.y;
	mov.u32 	%r12, %tid.y;
	mad.lo.s32 	%r2, %r10, %r11, %r12;
	setp.lt.s32	%p1, %r1, %r5;
	setp.lt.s32	%p2, %r2, %r6;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	cvt.rn.f32.s32	%f56, %r1;
	add.ftz.f32 	%f30, %f56, 0f3F000000;
	cvt.rn.f32.s32	%f57, %r2;
	add.ftz.f32 	%f31, %f57, 0f3F000000;
	add.ftz.f32 	%f42, %f30, 0fBF800000;
	add.ftz.f32 	%f19, %f31, 0f3F800000;
	add.ftz.f32 	%f48, %f30, 0f00000000;
	add.ftz.f32 	%f54, %f30, 0f3F800000;
	add.ftz.f32 	%f37, %f31, 0f00000000;
	add.ftz.f32 	%f55, %f31, 0fBF800000;
	// inline asm
	tex.2d.v4.f32.f32 {%f2, %f3, %f4, %f5}, [texture0_RECT, {%f42, %f19}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f8, %f9, %f10, %f11}, [texture0_RECT, {%f48, %f19}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f14, %f15, %f16, %f17}, [texture0_RECT, {%f54, %f19}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f20, %f21, %f22, %f23}, [texture0_RECT, {%f42, %f37}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f26, %f27, %f28, %f29}, [texture0_RECT, {%f30, %f31}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f32, %f33, %f34, %f35}, [texture0_RECT, {%f54, %f37}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f38, %f39, %f40, %f41}, [texture0_RECT, {%f42, %f55}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f44, %f45, %f46, %f47}, [texture0_RECT, {%f48, %f55}];
	// inline asm
	// inline asm
	tex.2d.v4.f32.f32 {%f50, %f51, %f52, %f53}, [texture0_RECT, {%f54, %f55}];
	// inline asm
	sub.ftz.f32 	%f58, %f4, %f10;
	sub.ftz.f32 	%f59, %f3, %f9;
	sub.ftz.f32 	%f60, %f2, %f8;
	sub.ftz.f32 	%f61, %f4, %f16;
	sub.ftz.f32 	%f62, %f3, %f15;
	sub.ftz.f32 	%f63, %f2, %f14;
	abs.ftz.f32 	%f64, %f58;
	abs.ftz.f32 	%f65, %f59;
	abs.ftz.f32 	%f66, %f60;
	abs.ftz.f32 	%f67, %f61;
	abs.ftz.f32 	%f68, %f62;
	abs.ftz.f32 	%f69, %f63;
	add.ftz.f32 	%f70, %f67, %f64;
	add.ftz.f32 	%f71, %f68, %f65;
	add.ftz.f32 	%f72, %f69, %f66;
	add.ftz.f32 	%f73, %f70, %f71;
	add.ftz.f32 	%f74, %f73, %f72;
	sub.ftz.f32 	%f75, %f22, %f28;
	sub.ftz.f32 	%f76, %f21, %f27;
	sub.ftz.f32 	%f77, %f20, %f26;
	sub.ftz.f32 	%f78, %f22, %f34;
	sub.ftz.f32 	%f79, %f21, %f33;
	sub.ftz.f32 	%f80, %f20, %f32;
	abs.ftz.f32 	%f81, %f75;
	abs.ftz.f32 	%f82, %f76;
	abs.ftz.f32 	%f83, %f77;
	abs.ftz.f32 	%f84, %f78;
	abs.ftz.f32 	%f85, %f79;
	abs.ftz.f32 	%f86, %f80;
	add.ftz.f32 	%f87, %f84, %f81;
	add.ftz.f32 	%f88, %f85, %f82;
	add.ftz.f32 	%f89, %f86, %f83;
	add.ftz.f32 	%f90, %f87, %f88;
	add.ftz.f32 	%f91, %f90, %f89;
	sub.ftz.f32 	%f92, %f40, %f46;
	sub.ftz.f32 	%f93, %f39, %f45;
	sub.ftz.f32 	%f94, %f38, %f44;
	sub.ftz.f32 	%f95, %f40, %f52;
	sub.ftz.f32 	%f96, %f39, %f51;
	sub.ftz.f32 	%f97, %f38, %f50;
	abs.ftz.f32 	%f98, %f92;
	abs.ftz.f32 	%f99, %f93;
	abs.ftz.f32 	%f100, %f94;
	abs.ftz.f32 	%f101, %f95;
	abs.ftz.f32 	%f102, %f96;
	abs.ftz.f32 	%f103, %f97;
	add.ftz.f32 	%f104, %f101, %f98;
	add.ftz.f32 	%f105, %f102, %f99;
	add.ftz.f32 	%f106, %f103, %f100;
	add.ftz.f32 	%f107, %f104, %f105;
	add.ftz.f32 	%f108, %f107, %f106;
	add.ftz.f32 	%f109, %f4, %f10;
	add.ftz.f32 	%f110, %f3, %f9;
	add.ftz.f32 	%f111, %f2, %f8;
	add.ftz.f32 	%f112, %f109, %f74;
	add.ftz.f32 	%f113, %f110, %f91;
	add.ftz.f32 	%f114, %f111, %f108;
	add.ftz.f32 	%f115, %f22, %f28;
	add.ftz.f32 	%f116, %f21, %f27;
	add.ftz.f32 	%f117, %f20, %f26;
	add.ftz.f32 	%f118, %f115, %f34;
	add.ftz.f32 	%f119, %f116, %f33;
	add.ftz.f32 	%f120, %f117, %f32;
	add.ftz.f32 	%f121, %f40, %f46;
	add.ftz.f32 	%f122, %f39, %f45;
	add.ftz.f32 	%f123, %f38, %f44;
	add.ftz.f32 	%f124, %f121, %f52;
	add.ftz.f32 	%f125, %f122, %f51;
	add.ftz.f32 	%f126, %f123, %f50;
	sub.ftz.f32 	%f127, %f118, %f112;
	sub.ftz.f32 	%f128, %f119, %f113;
	sub.ftz.f32 	%f129, %f120, %f114;
	abs.ftz.f32 	%f130, %f127;
	abs.ftz.f32 	%f131, %f128;
	abs.ftz.f32 	%f132, %f129;
	mul.ftz.f32 	%f133, %f131, 0f3EAAAAAB;
	fma.rn.ftz.f32 	%f134, %f130, 0f3EAAAAAB, %f133;
	fma.rn.ftz.f32 	%f135, %f132, 0f3EAAAAAB, %f134;
	sub.ftz.f32 	%f136, %f118, %f124;
	sub.ftz.f32 	%f137, %f119, %f125;
	sub.ftz.f32 	%f138, %f120, %f126;
	abs.ftz.f32 	%f139, %f136;
	abs.ftz.f32 	%f140, %f137;
	abs.ftz.f32 	%f141, %f138;
	mul.ftz.f32 	%f142, %f140, 0f3EAAAAAB;
	fma.rn.ftz.f32 	%f143, %f139, 0f3EAAAAAB, %f142;
	fma.rn.ftz.f32 	%f144, %f141, 0f3EAAAAAB, %f143;
	setp.lt.ftz.f32	%p4, %f74, 0f3EB33333;
	selp.f32	%f145, 0f3F800000, 0f00000000, %p4;
	setp.lt.ftz.f32	%p5, %f91, 0f3EB33333;
	selp.f32	%f146, 0f3F800000, 0f00000000, %p5;
	setp.lt.ftz.f32	%p6, %f108, 0f3EB33333;
	selp.f32	%f147, 0f3F800000, 0f00000000, %p6;
	setp.ltu.ftz.f32	%p7, %f135, 0f3D851EB8;
	selp.f32	%f148, 0f00000000, 0f3F800000, %p7;
	setp.ltu.ftz.f32	%p8, %f144, 0f3D851EB8;
	selp.f32	%f149, 0f00000000, 0f3F800000, %p8;
	mul.ftz.f32 	%f150, %f148, %f145;
	mul.ftz.f32 	%f151, %f149, %f146;
	mul.ftz.f32 	%f152, %f148, %f147;
	mul.ftz.f32 	%f153, %f150, %f151;
	mul.ftz.f32 	%f1, %f153, %f152;
	mad.lo.s32 	%r13, %r2, %r3, %r1;
	cvt.s64.s32	%rd2, %r13;
	setp.eq.s32	%p9, %r4, 0;
	@%p9 bra 	BB0_3;

	shl.b64 	%rd22, %rd2, 4;
	add.s64 	%rd23, %rd1, %rd22;
	st.global.v4.f32 	[%rd23], {%f1, %f1, %f1, %f1};
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd24, %rd2, 3;
	add.s64 	%rd25, %rd1, %rd24;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f1;
	mov.b16 	%rs1, %temp;
}
	st.global.v4.u16 	[%rd25], {%rs1, %rs1, %rs1, %rs1};

BB0_4:
	ret;
}


