//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry FillWithColorKernel(
	.param .u64 FillWithColorKernel_param_0,
	.param .u32 FillWithColorKernel_param_1,
	.param .u32 FillWithColorKernel_param_2,
	.param .u32 FillWithColorKernel_param_3,
	.param .u32 FillWithColorKernel_param_4,
	.param .u32 FillWithColorKernel_param_5,
	.param .u32 FillWithColorKernel_param_6,
	.param .align 16 .b8 FillWithColorKernel_param_7[16]
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<18>;
	.reg .f32 	%f<5>;
	.reg .s64 	%rd<8>;


	ld.param.u64 	%rd3, [FillWithColorKernel_param_0];
	ld.param.u32 	%r3, [FillWithColorKernel_param_1];
	ld.param.u32 	%r4, [FillWithColorKernel_param_2];
	ld.param.u32 	%r5, [FillWithColorKernel_param_3];
	ld.param.u32 	%r6, [FillWithColorKernel_param_4];
	ld.param.u32 	%r7, [FillWithColorKernel_param_5];
	ld.param.u32 	%r8, [FillWithColorKernel_param_6];
	ld.param.f32 	%f4, [FillWithColorKernel_param_7+12];
	ld.param.f32 	%f3, [FillWithColorKernel_param_7+8];
	ld.param.f32 	%f2, [FillWithColorKernel_param_7+4];
	ld.param.f32 	%f1, [FillWithColorKernel_param_7];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r11, %tid.x;
	mad.lo.s32 	%r1, %r9, %r10, %r11;
	mov.u32 	%r12, %ntid.y;
	mov.u32 	%r13, %ctaid.y;
	mov.u32 	%r14, %tid.y;
	mad.lo.s32 	%r2, %r12, %r13, %r14;
	setp.lt.s32	%p1, %r1, %r7;
	setp.lt.s32	%p2, %r2, %r8;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_4;
	bra.uni 	BB0_1;

BB0_1:
	add.s32 	%r15, %r2, %r6;
	add.s32 	%r16, %r1, %r5;
	mad.lo.s32 	%r17, %r15, %r3, %r16;
	cvt.s64.s32	%rd2, %r17;
	setp.eq.s32	%p4, %r4, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd4, %rd2, 4;
	add.s64 	%rd5, %rd1, %rd4;
	st.global.v4.f32 	[%rd5], {%f1, %f2, %f3, %f4};
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd6, %rd2, 3;
	add.s64 	%rd7, %rd1, %rd6;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f1;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f2;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f3;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f4;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd7], {%rs1, %rs2, %rs3, %rs4};

BB0_4:
	ret;
}


