//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry FieldReverseKernel(
	.param .u64 FieldReverseKernel_param_0,
	.param .u32 FieldReverseKernel_param_1,
	.param .u64 FieldReverseKernel_param_2,
	.param .u32 FieldReverseKernel_param_3,
	.param .u32 FieldReverseKernel_param_4,
	.param .u32 FieldReverseKernel_param_5,
	.param .u32 FieldReverseKernel_param_6
)
{
	.reg .pred 	%p<6>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<19>;
	.reg .f32 	%f<21>;
	.reg .s64 	%rd<15>;


	ld.param.u64 	%rd5, [FieldReverseKernel_param_0];
	ld.param.u32 	%r3, [FieldReverseKernel_param_1];
	ld.param.u64 	%rd6, [FieldReverseKernel_param_2];
	ld.param.u32 	%r4, [FieldReverseKernel_param_3];
	ld.param.u32 	%r5, [FieldReverseKernel_param_4];
	ld.param.u32 	%r6, [FieldReverseKernel_param_5];
	ld.param.u32 	%r7, [FieldReverseKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	add.s32 	%r14, %r2, -1;
	mov.u32 	%r15, 0;
	max.s32 	%r16, %r14, %r15;
	mad.lo.s32 	%r17, %r16, %r3, %r1;
	cvt.s64.s32	%rd3, %r17;
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd8];
	mov.f32 	%f20, %f16;
	mov.f32 	%f19, %f15;
	mov.f32 	%f18, %f14;
	mov.f32 	%f17, %f13;
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f17, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f18, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f19, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f20, %temp;
	}

BB0_4:
	mad.lo.s32 	%r18, %r2, %r4, %r1;
	cvt.s64.s32	%rd4, %r18;
	@%p4 bra 	BB0_6;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f17, %f18, %f19, %f20};
	bra.uni 	BB0_7;

BB0_6:
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f17;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f18;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f19;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f20;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs9, %rs10, %rs11, %rs12};

BB0_7:
	ret;
}


