//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry CreateShadowMask(
	.param .u64 CreateShadowMask_param_0,
	.param .u32 CreateShadowMask_param_1,
	.param .u32 CreateShadowMask_param_2,
	.param .u32 CreateShadowMask_param_3,
	.param .u64 CreateShadowMask_param_4,
	.param .u32 CreateShadowMask_param_5,
	.param .u32 CreateShadowMask_param_6,
	.param .u32 CreateShadowMask_param_7,
	.param .u32 CreateShadowMask_param_8,
	.param .u32 CreateShadowMask_param_9,
	.param .u32 CreateShadowMask_param_10
)
{
	.reg .pred 	%p<12>;
	.reg .s16 	%rs<9>;
	.reg .s32 	%r<22>;
	.reg .f32 	%f<22>;
	.reg .s64 	%rd<12>;


	ld.param.u64 	%rd4, [CreateShadowMask_param_0];
	ld.param.u32 	%r5, [CreateShadowMask_param_1];
	ld.param.u32 	%r6, [CreateShadowMask_param_2];
	ld.param.u32 	%r7, [CreateShadowMask_param_3];
	ld.param.u64 	%rd3, [CreateShadowMask_param_4];
	ld.param.u32 	%r8, [CreateShadowMask_param_5];
	ld.param.u32 	%r12, [CreateShadowMask_param_6];
	ld.param.u32 	%r13, [CreateShadowMask_param_7];
	ld.param.u32 	%r9, [CreateShadowMask_param_8];
	ld.param.u32 	%r10, [CreateShadowMask_param_9];
	ld.param.u32 	%r11, [CreateShadowMask_param_10];
	cvta.to.global.u64 	%rd1, %rd4;
	mov.u32 	%r14, %ntid.x;
	mov.u32 	%r15, %ctaid.x;
	mov.u32 	%r16, %tid.x;
	mad.lo.s32 	%r1, %r14, %r15, %r16;
	mov.u32 	%r17, %ntid.y;
	mov.u32 	%r18, %ctaid.y;
	mov.u32 	%r19, %tid.y;
	mad.lo.s32 	%r2, %r17, %r18, %r19;
	setp.lt.s32	%p1, %r1, %r12;
	setp.lt.s32	%p2, %r2, %r13;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_8;
	bra.uni 	BB0_1;

BB0_1:
	sub.s32 	%r3, %r1, %r10;
	setp.gt.s32	%p4, %r3, -1;
	setp.lt.s32	%p5, %r3, %r6;
	and.pred  	%p6, %p4, %p5;
	sub.s32 	%r4, %r2, %r11;
	setp.gt.s32	%p7, %r4, -1;
	and.pred  	%p8, %p6, %p7;
	setp.lt.s32	%p9, %r4, %r7;
	and.pred  	%p10, %p8, %p9;
	@%p10 bra 	BB0_3;

	mov.f32 	%f21, 0f00000000;
	bra.uni 	BB0_7;

BB0_3:
	mad.lo.s32 	%r20, %r4, %r5, %r3;
	cvt.s64.s32	%rd2, %r20;
	setp.eq.s32	%p11, %r9, 0;
	@%p11 bra 	BB0_5;

	shl.b64 	%rd5, %rd2, 4;
	add.s64 	%rd6, %rd1, %rd5;
	ld.global.v4.f32 	{%f16, %f17, %f18, %f19}, [%rd6];
	mov.f32 	%f20, %f19;
	mov.f32 	%f3, %f18;
	mov.f32 	%f2, %f17;
	mov.f32 	%f1, %f16;
	bra.uni 	BB0_6;

BB0_5:
	shl.b64 	%rd7, %rd2, 3;
	add.s64 	%rd8, %rd1, %rd7;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd8];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f20, %temp;
	}

BB0_6:
	mov.f32 	%f21, %f20;

BB0_7:
	cvta.to.global.u64 	%rd9, %rd3;
	mad.lo.s32 	%r21, %r2, %r8, %r1;
	mul.wide.s32 	%rd10, %r21, 4;
	add.s64 	%rd11, %rd9, %rd10;
	st.global.f32 	[%rd11], %f21;

BB0_8:
	ret;
}

.visible .entry CompositeShadowMask(
	.param .u64 CompositeShadowMask_param_0,
	.param .u32 CompositeShadowMask_param_1,
	.param .u32 CompositeShadowMask_param_2,
	.param .u32 CompositeShadowMask_param_3,
	.param .u64 CompositeShadowMask_param_4,
	.param .u32 CompositeShadowMask_param_5,
	.param .u64 CompositeShadowMask_param_6,
	.param .u32 CompositeShadowMask_param_7,
	.param .u32 CompositeShadowMask_param_8,
	.param .u32 CompositeShadowMask_param_9,
	.param .u32 CompositeShadowMask_param_10,
	.param .u32 CompositeShadowMask_param_11,
	.param .u32 CompositeShadowMask_param_12,
	.param .f32 CompositeShadowMask_param_13,
	.param .f32 CompositeShadowMask_param_14,
	.param .f32 CompositeShadowMask_param_15,
	.param .f32 CompositeShadowMask_param_16,
	.param .u32 CompositeShadowMask_param_17
)
{
	.reg .pred 	%p<15>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<25>;
	.reg .f32 	%f<72>;
	.reg .s64 	%rd<19>;


	ld.param.u64 	%rd6, [CompositeShadowMask_param_0];
	ld.param.u32 	%r5, [CompositeShadowMask_param_1];
	ld.param.u32 	%r6, [CompositeShadowMask_param_2];
	ld.param.u32 	%r7, [CompositeShadowMask_param_3];
	ld.param.u64 	%rd5, [CompositeShadowMask_param_4];
	ld.param.u32 	%r8, [CompositeShadowMask_param_5];
	ld.param.u64 	%rd7, [CompositeShadowMask_param_6];
	ld.param.u32 	%r9, [CompositeShadowMask_param_7];
	ld.param.u32 	%r14, [CompositeShadowMask_param_8];
	ld.param.u32 	%r15, [CompositeShadowMask_param_9];
	ld.param.u32 	%r10, [CompositeShadowMask_param_10];
	ld.param.u32 	%r11, [CompositeShadowMask_param_11];
	ld.param.u32 	%r12, [CompositeShadowMask_param_12];
	ld.param.f32 	%f68, [CompositeShadowMask_param_13];
	ld.param.f32 	%f69, [CompositeShadowMask_param_14];
	ld.param.f32 	%f70, [CompositeShadowMask_param_15];
	ld.param.f32 	%f35, [CompositeShadowMask_param_16];
	ld.param.u32 	%r13, [CompositeShadowMask_param_17];
	cvta.to.global.u64 	%rd1, %rd7;
	cvta.to.global.u64 	%rd2, %rd6;
	mov.u32 	%r16, %ntid.x;
	mov.u32 	%r17, %ctaid.x;
	mov.u32 	%r18, %tid.x;
	mad.lo.s32 	%r1, %r16, %r17, %r18;
	mov.u32 	%r19, %ntid.y;
	mov.u32 	%r20, %ctaid.y;
	mov.u32 	%r21, %tid.y;
	mad.lo.s32 	%r2, %r19, %r20, %r21;
	setp.lt.s32	%p1, %r1, %r14;
	setp.lt.s32	%p2, %r2, %r15;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB1_14;
	bra.uni 	BB1_1;

BB1_1:
	cvta.to.global.u64 	%rd8, %rd5;
	mad.lo.s32 	%r22, %r2, %r8, %r1;
	mul.wide.s32 	%rd9, %r22, 4;
	add.s64 	%rd10, %rd8, %rd9;
	ld.global.f32 	%f36, [%rd10];
	mul.ftz.f32 	%f71, %f36, %f35;
	setp.ne.s32	%p4, %r13, 0;
	@%p4 bra 	BB1_11;

	sub.s32 	%r3, %r1, %r10;
	setp.gt.s32	%p5, %r3, -1;
	setp.lt.s32	%p6, %r3, %r6;
	and.pred  	%p7, %p5, %p6;
	sub.s32 	%r4, %r2, %r11;
	setp.gt.s32	%p8, %r4, -1;
	and.pred  	%p9, %p7, %p8;
	setp.lt.s32	%p10, %r4, %r7;
	and.pred  	%p11, %p9, %p10;
	@%p11 bra 	BB1_4;

	mov.f32 	%f67, 0f00000000;
	mov.f32 	%f66, %f67;
	mov.f32 	%f65, %f67;
	mov.f32 	%f64, %f67;
	bra.uni 	BB1_8;

BB1_4:
	mad.lo.s32 	%r23, %r4, %r5, %r3;
	cvt.s64.s32	%rd3, %r23;
	setp.eq.s32	%p12, %r12, 0;
	@%p12 bra 	BB1_6;

	shl.b64 	%rd11, %rd3, 4;
	add.s64 	%rd12, %rd2, %rd11;
	ld.global.v4.f32 	{%f41, %f42, %f43, %f44}, [%rd12];
	mov.f32 	%f63, %f44;
	mov.f32 	%f62, %f43;
	mov.f32 	%f61, %f42;
	mov.f32 	%f60, %f41;
	bra.uni 	BB1_7;

BB1_6:
	shl.b64 	%rd13, %rd3, 3;
	add.s64 	%rd14, %rd2, %rd13;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd14];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f60, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f61, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f62, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f63, %temp;
	}

BB1_7:
	mov.f32 	%f64, %f60;
	mov.f32 	%f65, %f61;
	mov.f32 	%f66, %f62;
	mov.f32 	%f67, %f63;

BB1_8:
	cvt.ftz.sat.f32.f32	%f22, %f67;
	mov.f32 	%f45, 0f3F800000;
	sub.ftz.f32 	%f46, %f45, %f22;
	cvt.ftz.sat.f32.f32	%f47, %f71;
	mul.ftz.f32 	%f23, %f47, %f46;
	add.ftz.f32 	%f71, %f23, %f22;
	add.ftz.f32 	%f48, %f71, 0fB70637BD;
	setp.gtu.ftz.f32	%p13, %f48, 0f00000000;
	@%p13 bra 	BB1_10;

	mov.f32 	%f71, 0f00000000;
	mov.f32 	%f70, %f71;
	mov.f32 	%f69, %f71;
	mov.f32 	%f68, %f71;
	bra.uni 	BB1_11;

BB1_10:
	rcp.approx.ftz.f32 	%f53, %f71;
	mul.ftz.f32 	%f54, %f23, %f68;
	fma.rn.ftz.f32 	%f55, %f64, %f22, %f54;
	mul.ftz.f32 	%f68, %f55, %f53;
	mul.ftz.f32 	%f56, %f23, %f69;
	fma.rn.ftz.f32 	%f57, %f65, %f22, %f56;
	mul.ftz.f32 	%f69, %f57, %f53;
	mul.ftz.f32 	%f58, %f23, %f70;
	fma.rn.ftz.f32 	%f59, %f66, %f22, %f58;
	mul.ftz.f32 	%f70, %f59, %f53;

BB1_11:
	mad.lo.s32 	%r24, %r2, %r9, %r1;
	cvt.s64.s32	%rd4, %r24;
	setp.eq.s32	%p14, %r12, 0;
	@%p14 bra 	BB1_13;

	shl.b64 	%rd15, %rd4, 4;
	add.s64 	%rd16, %rd1, %rd15;
	st.global.v4.f32 	[%rd16], {%f68, %f69, %f70, %f71};
	bra.uni 	BB1_14;

BB1_13:
	shl.b64 	%rd17, %rd4, 3;
	add.s64 	%rd18, %rd1, %rd17;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f71;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f70;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f69;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f68;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd18], {%rs12, %rs11, %rs10, %rs9};

BB1_14:
	ret;
}


