//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel(
	.param .u64 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_0,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_1,
	.param .u64 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_2,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_3,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_4,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_5,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_6
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<19>;
	.reg .f32 	%f<29>;
	.reg .s64 	%rd<12>;


	ld.param.u64 	%rd5, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_0];
	ld.param.u32 	%r3, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_1];
	ld.param.u64 	%rd4, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_2];
	ld.param.u32 	%r4, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_3];
	ld.param.u32 	%r5, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_4];
	ld.param.u32 	%r6, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_5];
	ld.param.u32 	%r7, [PixelFormatConvert_BGRA_4444_32f_to_RGBX_4444_8uKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB0_5;
	bra.uni 	BB0_1;

BB0_1:
	cvta.to.global.u64 	%rd2, %rd4;
	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32	%rd3, %r14;
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB0_3;

	shl.b64 	%rd6, %rd3, 4;
	add.s64 	%rd7, %rd1, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd7];
	mov.f32 	%f28, %f16;
	mov.f32 	%f27, %f15;
	mov.f32 	%f26, %f14;
	mov.f32 	%f25, %f13;
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd8, %rd3, 3;
	add.s64 	%rd9, %rd1, %rd8;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd9];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f25, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f26, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f27, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f28, %temp;
	}

BB0_4:
	cvt.ftz.sat.f32.f32	%f17, %f28;
	mul.ftz.f32 	%f18, %f17, 0f437F0000;
	mad.lo.s32 	%r15, %r2, %r4, %r1;
	mul.wide.s32 	%rd10, %r15, 4;
	add.s64 	%rd11, %rd2, %rd10;
	cvt.ftz.sat.f32.f32	%f19, %f27;
	fma.rn.ftz.f32 	%f20, %f19, %f18, 0f3F000000;
	cvt.rzi.ftz.u32.f32	%r16, %f20;
	cvt.ftz.sat.f32.f32	%f21, %f26;
	fma.rn.ftz.f32 	%f22, %f21, %f18, 0f3F000000;
	cvt.rzi.ftz.u32.f32	%r17, %f22;
	cvt.ftz.sat.f32.f32	%f23, %f25;
	fma.rn.ftz.f32 	%f24, %f23, %f18, 0f3F000000;
	cvt.rzi.ftz.u32.f32	%r18, %f24;
	cvt.u16.u32	%rs9, %r18;
	cvt.u16.u32	%rs10, %r17;
	cvt.u16.u32	%rs11, %r16;
	mov.u16 	%rs12, 255;
	st.global.v4.u8 	[%rd11], {%rs11, %rs10, %rs9, %rs12};

BB0_5:
	ret;
}

.visible .entry PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel(
	.param .u64 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_0,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_1,
	.param .u64 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_2,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_3,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_4,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_5,
	.param .u32 PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_6
)
{
	.reg .pred 	%p<5>;
	.reg .s16 	%rs<9>;
	.reg .s32 	%r<25>;
	.reg .f32 	%f<29>;
	.reg .s64 	%rd<12>;


	ld.param.u64 	%rd5, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_0];
	ld.param.u32 	%r3, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_1];
	ld.param.u64 	%rd4, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_2];
	ld.param.u32 	%r4, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_3];
	ld.param.u32 	%r5, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_4];
	ld.param.u32 	%r6, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_5];
	ld.param.u32 	%r7, [PixelFormatConvert_BGRA_4444_32f_to_BGR10uX2uKernel_param_6];
	cvta.to.global.u64 	%rd1, %rd5;
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r2, %r11, %r12, %r13;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB1_5;
	bra.uni 	BB1_1;

BB1_1:
	cvta.to.global.u64 	%rd2, %rd4;
	mad.lo.s32 	%r14, %r2, %r3, %r1;
	cvt.s64.s32	%rd3, %r14;
	setp.eq.s32	%p4, %r5, 0;
	@%p4 bra 	BB1_3;

	shl.b64 	%rd6, %rd3, 4;
	add.s64 	%rd7, %rd1, %rd6;
	ld.global.v4.f32 	{%f13, %f14, %f15, %f16}, [%rd7];
	mov.f32 	%f28, %f16;
	mov.f32 	%f27, %f15;
	mov.f32 	%f26, %f14;
	mov.f32 	%f25, %f13;
	bra.uni 	BB1_4;

BB1_3:
	shl.b64 	%rd8, %rd3, 3;
	add.s64 	%rd9, %rd1, %rd8;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd9];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f25, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f26, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f27, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f28, %temp;
	}

BB1_4:
	cvt.ftz.sat.f32.f32	%f17, %f28;
	mul.ftz.f32 	%f18, %f17, 0f447FC000;
	cvt.ftz.sat.f32.f32	%f19, %f25;
	fma.rn.ftz.f32 	%f20, %f19, %f18, 0f3F000000;
	cvt.rzi.ftz.u32.f32	%r15, %f20;
	shl.b32 	%r16, %r15, 22;
	cvt.ftz.sat.f32.f32	%f21, %f26;
	fma.rn.ftz.f32 	%f22, %f21, %f18, 0f3F000000;
	cvt.rzi.ftz.u32.f32	%r17, %f22;
	shl.b32 	%r18, %r17, 12;
	cvt.ftz.sat.f32.f32	%f23, %f27;
	fma.rn.ftz.f32 	%f24, %f23, %f18, 0f3F000000;
	cvt.rzi.ftz.u32.f32	%r19, %f24;
	shl.b32 	%r20, %r19, 2;
	or.b32  	%r21, %r16, %r18;
	or.b32  	%r22, %r21, %r20;
	or.b32  	%r23, %r22, 3;
	mad.lo.s32 	%r24, %r2, %r4, %r1;
	mul.wide.s32 	%rd10, %r24, 4;
	add.s64 	%rd11, %rd2, %rd10;
	st.global.u32 	[%rd11], %r23;

BB1_5:
	ret;
}


