//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref inSrcTexture;

.visible .entry ShearHorizontalKernel(
	.param .u64 ShearHorizontalKernel_param_0,
	.param .u32 ShearHorizontalKernel_param_1,
	.param .u64 ShearHorizontalKernel_param_2,
	.param .u32 ShearHorizontalKernel_param_3,
	.param .u32 ShearHorizontalKernel_param_4,
	.param .u32 ShearHorizontalKernel_param_5,
	.param .u32 ShearHorizontalKernel_param_6,
	.param .u32 ShearHorizontalKernel_param_7,
	.param .f32 ShearHorizontalKernel_param_8,
	.param .u32 ShearHorizontalKernel_param_9
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<17>;
	.reg .f32 	%f<43>;
	.reg .s64 	%rd<9>;


	ld.param.u32 	%r3, [ShearHorizontalKernel_param_1];
	ld.param.u64 	%rd3, [ShearHorizontalKernel_param_2];
	ld.param.u32 	%r6, [ShearHorizontalKernel_param_3];
	ld.param.u32 	%r7, [ShearHorizontalKernel_param_4];
	ld.param.u32 	%r4, [ShearHorizontalKernel_param_5];
	ld.param.u32 	%r5, [ShearHorizontalKernel_param_6];
	ld.param.f32 	%f15, [ShearHorizontalKernel_param_8];
	ld.param.u32 	%r8, [ShearHorizontalKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r11, %tid.x;
	mad.lo.s32 	%r1, %r9, %r10, %r11;
	mov.u32 	%r12, %ntid.y;
	mov.u32 	%r13, %ctaid.y;
	mov.u32 	%r14, %tid.y;
	mad.lo.s32 	%r2, %r12, %r13, %r14;
	cvt.rn.f32.s32	%f16, %r1;
	cvt.rn.f32.s32	%f1, %r2;
	mul.ftz.f32 	%f17, %f1, %f15;
	sub.ftz.f32 	%f18, %f16, %f17;
	cvt.rn.f32.s32	%f19, %r8;
	sub.ftz.f32 	%f2, %f18, %f19;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	mov.f32 	%f39, 0f00000000;
	mov.f32 	%f40, 0f00000000;
	mov.f32 	%f41, 0f00000000;
	mov.f32 	%f42, 0f00000000;
	@!%p3 bra 	BB0_7;
	bra.uni 	BB0_1;

BB0_1:
	setp.ltu.ftz.f32	%p4, %f2, 0f00000000;
	@%p4 bra 	BB0_4;

	add.s32 	%r15, %r5, -1;
	cvt.rn.f32.s32	%f28, %r15;
	setp.gtu.ftz.f32	%p5, %f2, %f28;
	@%p5 bra 	BB0_4;

	add.ftz.f32 	%f33, %f2, 0f00000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [inSrcTexture, {%f33, %f1}];
	// inline asm
	mov.f32 	%f42, %f32;
	mov.f32 	%f41, %f31;
	mov.f32 	%f40, %f30;
	mov.f32 	%f39, %f29;

BB0_4:
	mad.lo.s32 	%r16, %r2, %r4, %r1;
	cvt.s64.s32	%rd2, %r16;
	setp.eq.s32	%p6, %r3, 0;
	@%p6 bra 	BB0_6;

	shl.b64 	%rd5, %rd2, 4;
	add.s64 	%rd6, %rd1, %rd5;
	st.global.v4.f32 	[%rd6], {%f39, %f40, %f41, %f42};
	bra.uni 	BB0_7;

BB0_6:
	shl.b64 	%rd7, %rd2, 3;
	add.s64 	%rd8, %rd1, %rd7;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f42;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f41;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f40;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f39;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd8], {%rs4, %rs3, %rs2, %rs1};

BB0_7:
	ret;
}

.visible .entry ShearVerticalKernel(
	.param .u64 ShearVerticalKernel_param_0,
	.param .u32 ShearVerticalKernel_param_1,
	.param .u64 ShearVerticalKernel_param_2,
	.param .u32 ShearVerticalKernel_param_3,
	.param .u32 ShearVerticalKernel_param_4,
	.param .u32 ShearVerticalKernel_param_5,
	.param .u32 ShearVerticalKernel_param_6,
	.param .u32 ShearVerticalKernel_param_7,
	.param .f32 ShearVerticalKernel_param_8,
	.param .u32 ShearVerticalKernel_param_9
)
{
	.reg .pred 	%p<7>;
	.reg .s16 	%rs<5>;
	.reg .s32 	%r<17>;
	.reg .f32 	%f<43>;
	.reg .s64 	%rd<9>;


	ld.param.u32 	%r3, [ShearVerticalKernel_param_1];
	ld.param.u64 	%rd3, [ShearVerticalKernel_param_2];
	ld.param.u32 	%r6, [ShearVerticalKernel_param_3];
	ld.param.u32 	%r7, [ShearVerticalKernel_param_4];
	ld.param.u32 	%r4, [ShearVerticalKernel_param_5];
	ld.param.u32 	%r5, [ShearVerticalKernel_param_7];
	ld.param.f32 	%f15, [ShearVerticalKernel_param_8];
	ld.param.u32 	%r8, [ShearVerticalKernel_param_9];
	cvta.to.global.u64 	%rd1, %rd3;
	mov.u32 	%r9, %ntid.x;
	mov.u32 	%r10, %ctaid.x;
	mov.u32 	%r11, %tid.x;
	mad.lo.s32 	%r1, %r9, %r10, %r11;
	mov.u32 	%r12, %ntid.y;
	mov.u32 	%r13, %ctaid.y;
	mov.u32 	%r14, %tid.y;
	mad.lo.s32 	%r2, %r12, %r13, %r14;
	cvt.rn.f32.s32	%f16, %r2;
	cvt.rn.f32.s32	%f1, %r1;
	mul.ftz.f32 	%f17, %f1, %f15;
	sub.ftz.f32 	%f18, %f16, %f17;
	cvt.rn.f32.s32	%f19, %r8;
	sub.ftz.f32 	%f2, %f18, %f19;
	setp.lt.s32	%p1, %r1, %r6;
	setp.lt.s32	%p2, %r2, %r7;
	and.pred  	%p3, %p1, %p2;
	mov.f32 	%f39, 0f00000000;
	mov.f32 	%f40, 0f00000000;
	mov.f32 	%f41, 0f00000000;
	mov.f32 	%f42, 0f00000000;
	@!%p3 bra 	BB1_7;
	bra.uni 	BB1_1;

BB1_1:
	setp.ltu.ftz.f32	%p4, %f2, 0f00000000;
	@%p4 bra 	BB1_4;

	add.s32 	%r15, %r5, -1;
	cvt.rn.f32.s32	%f28, %r15;
	setp.gtu.ftz.f32	%p5, %f2, %f28;
	@%p5 bra 	BB1_4;

	add.ftz.f32 	%f33, %f1, 0f3F000000;
	add.ftz.f32 	%f34, %f2, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f29, %f30, %f31, %f32}, [inSrcTexture, {%f33, %f34}];
	// inline asm
	mov.f32 	%f42, %f32;
	mov.f32 	%f41, %f31;
	mov.f32 	%f40, %f30;
	mov.f32 	%f39, %f29;

BB1_4:
	mad.lo.s32 	%r16, %r2, %r4, %r1;
	cvt.s64.s32	%rd2, %r16;
	setp.eq.s32	%p6, %r3, 0;
	@%p6 bra 	BB1_6;

	shl.b64 	%rd5, %rd2, 4;
	add.s64 	%rd6, %rd1, %rd5;
	st.global.v4.f32 	[%rd6], {%f39, %f40, %f41, %f42};
	bra.uni 	BB1_7;

BB1_6:
	shl.b64 	%rd7, %rd2, 3;
	add.s64 	%rd8, %rd1, %rd7;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f42;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f41;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f40;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f39;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd8], {%rs4, %rs3, %rs2, %rs1};

BB1_7:
	ret;
}


