//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64

.global .texref ioBufTexture;

.visible .func  (.param .align 16 .b8 func_retval0[16]) _Z18UnpremultiplyPixel8PixelRGB(
	.param .align 16 .b8 _Z18UnpremultiplyPixel8PixelRGB_param_0[16]
)
{
	.reg .pred 	%p<2>;
	.reg .f32 	%f<24>;


	ld.param.f32 	%f11, [_Z18UnpremultiplyPixel8PixelRGB_param_0+8];
	ld.param.f32 	%f10, [_Z18UnpremultiplyPixel8PixelRGB_param_0+4];
	ld.param.f32 	%f9, [_Z18UnpremultiplyPixel8PixelRGB_param_0];
	ld.param.f32 	%f12, [_Z18UnpremultiplyPixel8PixelRGB_param_0+12];
	cvt.ftz.sat.f32.f32	%f20, %f12;
	add.ftz.f32 	%f13, %f20, 0fB70637BD;
	setp.gtu.ftz.f32	%p1, %f13, 0f00000000;
	@%p1 bra 	BB0_2;

	mov.f32 	%f23, 0f00000000;
	mov.f32 	%f22, %f23;
	mov.f32 	%f21, %f23;
	mov.f32 	%f20, %f23;
	bra.uni 	BB0_3;

BB0_2:
	mov.f32 	%f18, 0f3F800000;
	div.approx.ftz.f32 	%f19, %f18, %f20;
	mul.ftz.f32 	%f21, %f11, %f19;
	mul.ftz.f32 	%f22, %f10, %f19;
	mul.ftz.f32 	%f23, %f9, %f19;

BB0_3:
	st.param.f32	[func_retval0+0], %f23;
	st.param.f32	[func_retval0+4], %f22;
	st.param.f32	[func_retval0+8], %f21;
	st.param.f32	[func_retval0+12], %f20;
	ret;
}

.visible .entry DeinterlaceSamplerKernel(
	.param .u64 DeinterlaceSamplerKernel_param_0,
	.param .u64 DeinterlaceSamplerKernel_param_1,
	.param .u32 DeinterlaceSamplerKernel_param_2,
	.param .u32 DeinterlaceSamplerKernel_param_3,
	.param .u32 DeinterlaceSamplerKernel_param_4,
	.param .u32 DeinterlaceSamplerKernel_param_5,
	.param .u32 DeinterlaceSamplerKernel_param_6
)
{
	.reg .pred 	%p<68>;
	.reg .s16 	%rs<17>;
	.reg .s32 	%r<70>;
	.reg .f32 	%f<236>;
	.reg .s64 	%rd<37>;


	ld.param.u64 	%rd3, [DeinterlaceSamplerKernel_param_1];
	ld.param.u32 	%r3, [DeinterlaceSamplerKernel_param_2];
	ld.param.u32 	%r4, [DeinterlaceSamplerKernel_param_3];
	ld.param.u32 	%r5, [DeinterlaceSamplerKernel_param_4];
	ld.param.u32 	%r6, [DeinterlaceSamplerKernel_param_5];
	ld.param.u32 	%r7, [DeinterlaceSamplerKernel_param_6];
	mov.u32 	%r8, %ntid.x;
	mov.u32 	%r9, %ctaid.x;
	mov.u32 	%r10, %tid.x;
	mad.lo.s32 	%r1, %r8, %r9, %r10;
	mov.u32 	%r11, %ntid.y;
	mov.u32 	%r12, %ctaid.y;
	mov.u32 	%r13, %tid.y;
	mad.lo.s32 	%r14, %r11, %r12, %r13;
	shl.b32 	%r15, %r14, 1;
	setp.ne.s32	%p2, %r7, 0;
	selp.u32	%r16, 1, 0, %p2;
	add.s32 	%r2, %r15, %r16;
	setp.ge.s32	%p3, %r1, %r5;
	@%p3 bra 	BB1_65;

	cvta.to.global.u64 	%rd4, %rd3;
	setp.gt.s32	%p4, %r2, 0;
	add.s32 	%r17, %r2, 1;
	setp.lt.s32	%p5, %r17, %r6;
	and.pred  	%p1, %p4, %p5;
	setp.gt.s32	%p6, %r1, 0;
	and.pred  	%p7, %p1, %p6;
	add.s32 	%r18, %r1, 1;
	setp.lt.s32	%p8, %r18, %r5;
	and.pred  	%p9, %p7, %p8;
	mad.lo.s32 	%r19, %r2, %r3, %r1;
	mul.wide.s32 	%rd5, %r19, 16;
	add.s64 	%rd1, %rd4, %rd5;
	mul.wide.s32 	%rd6, %r19, 8;
	add.s64 	%rd2, %rd4, %rd6;
	@%p9 bra 	BB1_37;

	@%p1 bra 	BB1_11;

	or.b32  	%r20, %r2, %r7;
	setp.eq.s32	%p10, %r20, 0;
	@%p10 bra 	BB1_8;

	add.s32 	%r21, %r6, -1;
	setp.eq.s32	%p12, %r2, %r21;
	and.pred  	%p13, %p12, %p2;
	@!%p13 bra 	BB1_65;
	bra.uni 	BB1_5;

BB1_5:
	cvt.rn.f32.s32	%f113, %r1;
	add.ftz.f32 	%f111, %f113, 0f3F000000;
	cvt.rn.f32.s32	%f114, %r2;
	add.ftz.f32 	%f112, %f114, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f107, %f108, %f109, %f110}, [ioBufTexture, {%f111, %f112}];
	// inline asm
	setp.eq.s32	%p14, %r4, 0;
	@%p14 bra 	BB1_7;

	st.global.v4.f32 	[%rd1], {%f107, %f108, %f109, %f110};
	bra.uni 	BB1_65;

BB1_7:
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f110;
	mov.b16 	%rs1, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f109;
	mov.b16 	%rs2, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f108;
	mov.b16 	%rs3, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f107;
	mov.b16 	%rs4, %temp;
}
	st.global.v4.u16 	[%rd2], {%rs4, %rs3, %rs2, %rs1};
	bra.uni 	BB1_65;

BB1_8:
	cvt.rn.f32.s32	%f121, %r1;
	add.ftz.f32 	%f119, %f121, 0f3F000000;
	mov.f32 	%f120, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f115, %f116, %f117, %f118}, [ioBufTexture, {%f119, %f120}];
	// inline asm
	setp.eq.s32	%p15, %r4, 0;
	@%p15 bra 	BB1_10;

	st.global.v4.f32 	[%rd1], {%f115, %f116, %f117, %f118};
	bra.uni 	BB1_65;

BB1_10:
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f118;
	mov.b16 	%rs5, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f117;
	mov.b16 	%rs6, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f116;
	mov.b16 	%rs7, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f115;
	mov.b16 	%rs8, %temp;
}
	st.global.v4.u16 	[%rd2], {%rs8, %rs7, %rs6, %rs5};
	bra.uni 	BB1_65;

BB1_11:
	cvt.rn.f32.s32	%f134, %r1;
	add.ftz.f32 	%f132, %f134, 0f3F000000;
	cvt.rn.f32.s32	%f135, %r2;
	add.ftz.f32 	%f127, %f135, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f122, %f123, %f124, %f125}, [ioBufTexture, {%f132, %f127}];
	// inline asm
	mul.ftz.f32 	%f10, %f124, %f125;
	mul.ftz.f32 	%f11, %f123, %f125;
	mul.ftz.f32 	%f12, %f122, %f125;
	add.ftz.f32 	%f133, %f135, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f128, %f129, %f130, %f131}, [ioBufTexture, {%f132, %f133}];
	// inline asm
	mul.ftz.f32 	%f214, %f130, %f131;
	mul.ftz.f32 	%f213, %f129, %f131;
	mul.ftz.f32 	%f212, %f128, %f131;
	add.ftz.f32 	%f136, %f12, %f212;
	mul.ftz.f32 	%f17, %f136, 0f3F000000;
	add.ftz.f32 	%f137, %f11, %f213;
	mul.ftz.f32 	%f18, %f137, 0f3F000000;
	add.ftz.f32 	%f138, %f10, %f214;
	mul.ftz.f32 	%f19, %f138, 0f3F000000;
	add.ftz.f32 	%f139, %f125, %f131;
	mul.ftz.f32 	%f20, %f139, 0f3F000000;
	setp.gt.ftz.f32	%p16, %f12, %f212;
	mov.f32 	%f215, %f131;
	@%p16 bra 	BB1_14;

	setp.gt.ftz.f32	%p17, %f17, %f212;
	@%p17 bra 	BB1_16;

	setp.gt.ftz.f32	%p18, %f12, %f17;
	selp.f32	%f212, %f12, %f17, %p18;
	bra.uni 	BB1_16;

BB1_14:
	setp.gt.ftz.f32	%p19, %f212, %f17;
	@%p19 bra 	BB1_16;

	setp.gt.ftz.f32	%p20, %f12, %f17;
	selp.f32	%f212, %f17, %f12, %p20;

BB1_16:
	setp.gt.ftz.f32	%p21, %f11, %f213;
	@%p21 bra 	BB1_19;

	setp.gt.ftz.f32	%p22, %f18, %f213;
	@%p22 bra 	BB1_21;

	setp.gt.ftz.f32	%p23, %f11, %f18;
	selp.f32	%f213, %f11, %f18, %p23;
	bra.uni 	BB1_21;

BB1_19:
	setp.gt.ftz.f32	%p24, %f213, %f18;
	@%p24 bra 	BB1_21;

	setp.gt.ftz.f32	%p25, %f11, %f18;
	selp.f32	%f213, %f18, %f11, %p25;

BB1_21:
	setp.gt.ftz.f32	%p26, %f10, %f214;
	@%p26 bra 	BB1_24;

	setp.gt.ftz.f32	%p27, %f19, %f214;
	@%p27 bra 	BB1_26;

	setp.gt.ftz.f32	%p28, %f10, %f19;
	selp.f32	%f214, %f10, %f19, %p28;
	bra.uni 	BB1_26;

BB1_24:
	setp.gt.ftz.f32	%p29, %f214, %f19;
	@%p29 bra 	BB1_26;

	setp.gt.ftz.f32	%p30, %f10, %f19;
	selp.f32	%f214, %f19, %f10, %p30;

BB1_26:
	setp.gt.ftz.f32	%p31, %f125, %f131;
	@%p31 bra 	BB1_29;

	setp.gt.ftz.f32	%p32, %f20, %f131;
	@%p32 bra 	BB1_31;

	setp.gt.ftz.f32	%p33, %f125, %f20;
	selp.f32	%f215, %f125, %f20, %p33;
	bra.uni 	BB1_31;

BB1_29:
	setp.gt.ftz.f32	%p34, %f131, %f20;
	@%p34 bra 	BB1_31;

	setp.gt.ftz.f32	%p35, %f125, %f20;
	selp.f32	%f215, %f20, %f125, %p35;

BB1_31:
	cvt.ftz.sat.f32.f32	%f216, %f215;
	add.ftz.f32 	%f140, %f216, 0fB70637BD;
	setp.gtu.ftz.f32	%p36, %f140, 0f00000000;
	@%p36 bra 	BB1_33;

	mov.f32 	%f219, 0f00000000;
	mov.f32 	%f218, %f219;
	mov.f32 	%f217, %f219;
	mov.f32 	%f216, %f219;
	bra.uni 	BB1_34;

BB1_33:
	mov.f32 	%f145, 0f3F800000;
	div.approx.ftz.f32 	%f146, %f145, %f216;
	mul.ftz.f32 	%f217, %f214, %f146;
	mul.ftz.f32 	%f218, %f213, %f146;
	mul.ftz.f32 	%f219, %f212, %f146;

BB1_34:
	setp.eq.s32	%p37, %r4, 0;
	@%p37 bra 	BB1_36;

	mul.wide.s32 	%rd14, %r19, 16;
	add.s64 	%rd15, %rd4, %rd14;
	st.global.v4.f32 	[%rd15], {%f219, %f218, %f217, %f216};
	bra.uni 	BB1_65;

BB1_36:
	mul.wide.s32 	%rd17, %r19, 8;
	add.s64 	%rd18, %rd4, %rd17;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f216;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f217;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f218;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f219;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd18], {%rs12, %rs11, %rs10, %rs9};
	bra.uni 	BB1_65;

BB1_37:
	cvt.rn.f32.s32	%f183, %r1;
	add.ftz.f32 	%f169, %f183, 0fBF000000;
	cvt.rn.f32.s32	%f184, %r2;
	add.ftz.f32 	%f164, %f184, 0fBF000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f147, %f148, %f149, %f150}, [ioBufTexture, {%f169, %f164}];
	// inline asm
	mul.ftz.f32 	%f222, %f149, %f150;
	mul.ftz.f32 	%f221, %f148, %f150;
	mul.ftz.f32 	%f220, %f147, %f150;
	add.ftz.f32 	%f175, %f183, 0f3F000000;
	// inline asm
	tex.2d.v4.f32.f32 {%f153, %f154, %f155, %f156}, [ioBufTexture, {%f175, %f164}];
	// inline asm
	mul.ftz.f32 	%f46, %f155, %f156;
	mul.ftz.f32 	%f47, %f154, %f156;
	mul.ftz.f32 	%f48, %f153, %f156;
	add.ftz.f32 	%f181, %f183, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f159, %f160, %f161, %f162}, [ioBufTexture, {%f181, %f164}];
	// inline asm
	mul.ftz.f32 	%f51, %f161, %f162;
	mul.ftz.f32 	%f50, %f160, %f162;
	mul.ftz.f32 	%f49, %f159, %f162;
	add.ftz.f32 	%f182, %f184, 0f3FC00000;
	// inline asm
	tex.2d.v4.f32.f32 {%f165, %f166, %f167, %f168}, [ioBufTexture, {%f169, %f182}];
	// inline asm
	mul.ftz.f32 	%f55, %f167, %f168;
	mul.ftz.f32 	%f54, %f166, %f168;
	mul.ftz.f32 	%f53, %f165, %f168;
	// inline asm
	tex.2d.v4.f32.f32 {%f171, %f172, %f173, %f174}, [ioBufTexture, {%f175, %f182}];
	// inline asm
	mul.ftz.f32 	%f230, %f173, %f174;
	mul.ftz.f32 	%f229, %f172, %f174;
	mul.ftz.f32 	%f228, %f171, %f174;
	// inline asm
	tex.2d.v4.f32.f32 {%f177, %f178, %f179, %f180}, [ioBufTexture, {%f181, %f182}];
	// inline asm
	mul.ftz.f32 	%f226, %f179, %f180;
	mul.ftz.f32 	%f225, %f178, %f180;
	mul.ftz.f32 	%f224, %f177, %f180;
	sub.ftz.f32 	%f185, %f220, %f224;
	sub.ftz.f32 	%f186, %f221, %f225;
	sub.ftz.f32 	%f187, %f222, %f226;
	mul.ftz.f32 	%f188, %f186, %f186;
	fma.rn.ftz.f32 	%f189, %f187, %f187, %f188;
	fma.rn.ftz.f32 	%f190, %f185, %f185, %f189;
	sub.ftz.f32 	%f191, %f48, %f228;
	sub.ftz.f32 	%f192, %f47, %f229;
	sub.ftz.f32 	%f193, %f46, %f230;
	mul.ftz.f32 	%f194, %f192, %f192;
	fma.rn.ftz.f32 	%f195, %f193, %f193, %f194;
	fma.rn.ftz.f32 	%f65, %f191, %f191, %f195;
	sub.ftz.f32 	%f196, %f49, %f53;
	sub.ftz.f32 	%f197, %f50, %f54;
	sub.ftz.f32 	%f198, %f51, %f55;
	mul.ftz.f32 	%f199, %f197, %f197;
	fma.rn.ftz.f32 	%f200, %f198, %f198, %f199;
	fma.rn.ftz.f32 	%f66, %f196, %f196, %f200;
	setp.lt.ftz.f32	%p40, %f190, %f65;
	setp.lt.ftz.f32	%p41, %f190, %f66;
	and.pred  	%p42, %p40, %p41;
	mov.f32 	%f227, %f180;
	mov.f32 	%f223, %f150;
	mov.f32 	%f231, %f174;
	@%p42 bra 	BB1_39;

	setp.lt.ftz.f32	%p43, %f65, %f66;
	selp.f32	%f221, %f47, %f50, %p43;
	selp.f32	%f220, %f48, %f49, %p43;
	selp.f32	%f222, %f46, %f51, %p43;
	selp.f32	%f223, %f156, %f162, %p43;
	selp.f32	%f225, %f229, %f54, %p43;
	selp.f32	%f224, %f228, %f53, %p43;
	selp.f32	%f226, %f230, %f55, %p43;
	selp.f32	%f227, %f174, %f168, %p43;

BB1_39:
	add.ftz.f32 	%f201, %f220, %f224;
	mul.ftz.f32 	%f83, %f201, 0f3F000000;
	add.ftz.f32 	%f202, %f221, %f225;
	mul.ftz.f32 	%f84, %f202, 0f3F000000;
	add.ftz.f32 	%f203, %f222, %f226;
	mul.ftz.f32 	%f85, %f203, 0f3F000000;
	add.ftz.f32 	%f204, %f223, %f227;
	mul.ftz.f32 	%f86, %f204, 0f3F000000;
	setp.gt.ftz.f32	%p44, %f48, %f228;
	@%p44 bra 	BB1_42;

	setp.gt.ftz.f32	%p45, %f83, %f228;
	@%p45 bra 	BB1_44;

	setp.gt.ftz.f32	%p46, %f48, %f83;
	selp.f32	%f228, %f48, %f83, %p46;
	bra.uni 	BB1_44;

BB1_42:
	setp.gt.ftz.f32	%p47, %f228, %f83;
	@%p47 bra 	BB1_44;

	setp.gt.ftz.f32	%p48, %f48, %f83;
	selp.f32	%f228, %f83, %f48, %p48;

BB1_44:
	setp.gt.ftz.f32	%p49, %f47, %f229;
	@%p49 bra 	BB1_47;

	setp.gt.ftz.f32	%p50, %f84, %f229;
	@%p50 bra 	BB1_49;

	setp.gt.ftz.f32	%p51, %f47, %f84;
	selp.f32	%f229, %f47, %f84, %p51;
	bra.uni 	BB1_49;

BB1_47:
	setp.gt.ftz.f32	%p52, %f229, %f84;
	@%p52 bra 	BB1_49;

	setp.gt.ftz.f32	%p53, %f47, %f84;
	selp.f32	%f229, %f84, %f47, %p53;

BB1_49:
	setp.gt.ftz.f32	%p54, %f46, %f230;
	@%p54 bra 	BB1_52;

	setp.gt.ftz.f32	%p55, %f85, %f230;
	@%p55 bra 	BB1_54;

	setp.gt.ftz.f32	%p56, %f46, %f85;
	selp.f32	%f230, %f46, %f85, %p56;
	bra.uni 	BB1_54;

BB1_52:
	setp.gt.ftz.f32	%p57, %f230, %f85;
	@%p57 bra 	BB1_54;

	setp.gt.ftz.f32	%p58, %f46, %f85;
	selp.f32	%f230, %f85, %f46, %p58;

BB1_54:
	setp.gt.ftz.f32	%p59, %f156, %f174;
	@%p59 bra 	BB1_57;

	setp.gt.ftz.f32	%p60, %f86, %f174;
	@%p60 bra 	BB1_59;

	setp.gt.ftz.f32	%p61, %f156, %f86;
	selp.f32	%f231, %f156, %f86, %p61;
	bra.uni 	BB1_59;

BB1_57:
	setp.gt.ftz.f32	%p62, %f174, %f86;
	@%p62 bra 	BB1_59;

	setp.gt.ftz.f32	%p63, %f156, %f86;
	selp.f32	%f231, %f86, %f156, %p63;

BB1_59:
	cvt.ftz.sat.f32.f32	%f232, %f231;
	add.ftz.f32 	%f205, %f232, 0fB70637BD;
	setp.gtu.ftz.f32	%p64, %f205, 0f00000000;
	@%p64 bra 	BB1_61;

	mov.f32 	%f235, 0f00000000;
	mov.f32 	%f234, %f235;
	mov.f32 	%f233, %f235;
	mov.f32 	%f232, %f235;
	bra.uni 	BB1_62;

BB1_61:
	mov.f32 	%f210, 0f3F800000;
	div.approx.ftz.f32 	%f211, %f210, %f232;
	mul.ftz.f32 	%f233, %f230, %f211;
	mul.ftz.f32 	%f234, %f229, %f211;
	mul.ftz.f32 	%f235, %f228, %f211;

BB1_62:
	setp.eq.s32	%p65, %r4, 0;
	@%p65 bra 	BB1_64;

	mul.wide.s32 	%rd32, %r19, 16;
	add.s64 	%rd33, %rd4, %rd32;
	st.global.v4.f32 	[%rd33], {%f235, %f234, %f233, %f232};
	bra.uni 	BB1_65;

BB1_64:
	mul.wide.s32 	%rd35, %r19, 8;
	add.s64 	%rd36, %rd4, %rd35;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f232;
	mov.b16 	%rs13, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f233;
	mov.b16 	%rs14, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f234;
	mov.b16 	%rs15, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f235;
	mov.b16 	%rs16, %temp;
}
	st.global.v4.u16 	[%rd36], {%rs16, %rs15, %rs14, %rs13};

BB1_65:
	ret;
}


