//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry CropKernel(
	.param .u64 CropKernel_param_0,
	.param .u32 CropKernel_param_1,
	.param .u64 CropKernel_param_2,
	.param .u32 CropKernel_param_3,
	.param .u32 CropKernel_param_4,
	.param .u32 CropKernel_param_5,
	.param .u32 CropKernel_param_6,
	.param .u32 CropKernel_param_7,
	.param .u32 CropKernel_param_8,
	.param .u32 CropKernel_param_9,
	.param .u32 CropKernel_param_10,
	.param .u32 CropKernel_param_11,
	.param .u32 CropKernel_param_12,
	.param .f32 CropKernel_param_13,
	.param .f32 CropKernel_param_14
)
{
	.reg .pred 	%p<14>;
	.reg .s16 	%rs<13>;
	.reg .s32 	%r<33>;
	.reg .f32 	%f<33>;
	.reg .s64 	%rd<15>;
	.reg .f64 	%fd<11>;


	ld.param.u64 	%rd5, [CropKernel_param_0];
	ld.param.u32 	%r5, [CropKernel_param_1];
	ld.param.u64 	%rd6, [CropKernel_param_2];
	ld.param.u32 	%r6, [CropKernel_param_3];
	ld.param.u32 	%r7, [CropKernel_param_4];
	ld.param.u32 	%r8, [CropKernel_param_5];
	ld.param.u32 	%r9, [CropKernel_param_6];
	ld.param.u32 	%r10, [CropKernel_param_7];
	ld.param.u32 	%r11, [CropKernel_param_8];
	ld.param.u32 	%r12, [CropKernel_param_9];
	ld.param.u32 	%r13, [CropKernel_param_10];
	ld.param.u32 	%r14, [CropKernel_param_11];
	ld.param.u32 	%r15, [CropKernel_param_12];
	ld.param.f32 	%f18, [CropKernel_param_13];
	ld.param.f32 	%f19, [CropKernel_param_14];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r16, %ntid.x;
	mov.u32 	%r17, %ctaid.x;
	mov.u32 	%r18, %tid.x;
	mad.lo.s32 	%r19, %r16, %r17, %r18;
	add.s32 	%r1, %r19, %r13;
	mov.u32 	%r20, %ntid.y;
	mov.u32 	%r21, %ctaid.y;
	mov.u32 	%r22, %tid.y;
	mad.lo.s32 	%r23, %r20, %r21, %r22;
	add.s32 	%r2, %r23, %r12;
	or.b32  	%r24, %r23, %r19;
	setp.gt.s32	%p1, %r24, -1;
	setp.lt.s32	%p2, %r1, %r15;
	and.pred  	%p3, %p1, %p2;
	setp.lt.s32	%p4, %r2, %r14;
	and.pred  	%p5, %p3, %p4;
	@!%p5 bra 	BB0_11;
	bra.uni 	BB0_1;

BB0_1:
	mad.lo.s32 	%r25, %r2, %r5, %r1;
	cvt.s64.s32	%rd3, %r25;
	setp.eq.s32	%p6, %r7, 0;
	@%p6 bra 	BB0_3;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f20, %f21, %f22, %f23}, [%rd8];
	mov.f32 	%f31, %f23;
	mov.f32 	%f30, %f22;
	mov.f32 	%f29, %f21;
	mov.f32 	%f28, %f20;
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f28, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f29, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f30, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f31, %temp;
	}

BB0_4:
	sub.s32 	%r26, %r1, %r11;
	setp.lt.s32	%p7, %r1, %r11;
	selp.b32	%r27, 0, %r26, %p7;
	sub.s32 	%r28, %r9, %r1;
	setp.lt.s32	%p8, %r1, %r9;
	selp.b32	%r3, %r28, %r27, %p8;
	sub.s32 	%r29, %r2, %r10;
	setp.lt.s32	%p9, %r2, %r10;
	selp.b32	%r30, 0, %r29, %p9;
	sub.s32 	%r31, %r8, %r2;
	setp.lt.s32	%p10, %r2, %r8;
	selp.b32	%r4, %r31, %r30, %p10;
	setp.eq.s32	%p11, %r3, 0;
	mov.f32 	%f32, %f31;
	@%p11 bra 	BB0_6;

	cvt.rn.f32.s32	%f24, %r3;
	mul.ftz.f32 	%f25, %f24, %f18;
	cvt.ftz.f64.f32	%fd1, %f25;
	mov.f64 	%fd2, 0d3FF0000000000000;
	sub.f64 	%fd3, %fd2, %fd1;
	cvt.ftz.f64.f32	%fd4, %f31;
	mul.f64 	%fd5, %fd4, %fd3;
	cvt.rn.ftz.f32.f64	%f32, %fd5;

BB0_6:
	setp.eq.s32	%p12, %r4, 0;
	@%p12 bra 	BB0_8;

	cvt.rn.f32.s32	%f26, %r4;
	mul.ftz.f32 	%f27, %f26, %f19;
	cvt.ftz.f64.f32	%fd6, %f27;
	mov.f64 	%fd7, 0d3FF0000000000000;
	sub.f64 	%fd8, %fd7, %fd6;
	cvt.ftz.f64.f32	%fd9, %f32;
	mul.f64 	%fd10, %fd9, %fd8;
	cvt.rn.ftz.f32.f64	%f32, %fd10;

BB0_8:
	mad.lo.s32 	%r32, %r2, %r6, %r1;
	cvt.s64.s32	%rd4, %r32;
	@%p6 bra 	BB0_10;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	st.global.v4.f32 	[%rd12], {%f28, %f29, %f30, %f32};
	bra.uni 	BB0_11;

BB0_10:
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f32;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f28;
	mov.b16 	%rs10, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f29;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f30;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs10, %rs11, %rs12, %rs9};

BB0_11:
	ret;
}


