//
// Generated by NVIDIA NVVM Compiler
// Compiler built on Fri Jul 25 04:36:16 2014 (1406288176)
// Cuda compilation tools, release 6.5, V6.5.13
//

.version 4.1
.target sm_30
.address_size 64


.visible .entry CopyAlphaKernel(
	.param .u64 CopyAlphaKernel_param_0,
	.param .u32 CopyAlphaKernel_param_1,
	.param .u32 CopyAlphaKernel_param_2,
	.param .u32 CopyAlphaKernel_param_3,
	.param .u64 CopyAlphaKernel_param_4,
	.param .u32 CopyAlphaKernel_param_5,
	.param .u32 CopyAlphaKernel_param_6,
	.param .u32 CopyAlphaKernel_param_7,
	.param .u32 CopyAlphaKernel_param_8
)
{
	.reg .pred 	%p<15>;
	.reg .s16 	%rs<17>;
	.reg .s32 	%r<23>;
	.reg .f32 	%f<33>;
	.reg .s64 	%rd<19>;


	ld.param.u64 	%rd7, [CopyAlphaKernel_param_0];
	ld.param.u32 	%r4, [CopyAlphaKernel_param_1];
	ld.param.u32 	%r8, [CopyAlphaKernel_param_2];
	ld.param.u32 	%r9, [CopyAlphaKernel_param_3];
	ld.param.u64 	%rd8, [CopyAlphaKernel_param_4];
	ld.param.u32 	%r5, [CopyAlphaKernel_param_5];
	ld.param.u32 	%r6, [CopyAlphaKernel_param_6];
	ld.param.u32 	%r7, [CopyAlphaKernel_param_7];
	ld.param.u32 	%r10, [CopyAlphaKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd8;
	cvta.to.global.u64 	%rd2, %rd7;
	mov.u32 	%r11, %ntid.x;
	mov.u32 	%r12, %ctaid.x;
	mov.u32 	%r13, %tid.x;
	mad.lo.s32 	%r1, %r11, %r12, %r13;
	mov.u32 	%r14, %ntid.y;
	mov.u32 	%r15, %ctaid.y;
	mov.u32 	%r16, %tid.y;
	mad.lo.s32 	%r2, %r14, %r15, %r16;
	setp.lt.s32	%p1, %r1, %r8;
	setp.lt.s32	%p2, %r2, %r9;
	and.pred  	%p3, %p1, %p2;
	setp.lt.s32	%p4, %r2, %r10;
	and.pred  	%p5, %p3, %p4;
	@!%p5 bra 	BB0_20;
	bra.uni 	BB0_1;

BB0_1:
	mad.lo.s32 	%r17, %r2, %r4, %r1;
	cvt.s64.s32	%rd3, %r17;
	setp.eq.s32	%p6, %r6, 0;
	@%p6 bra 	BB0_3;

	shl.b64 	%rd9, %rd3, 4;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.f32 	{%f17, %f18, %f19, %f20}, [%rd10];
	mov.f32 	%f32, %f20;
	mov.f32 	%f31, %f19;
	mov.f32 	%f30, %f18;
	mov.f32 	%f29, %f17;
	bra.uni 	BB0_4;

BB0_3:
	shl.b64 	%rd11, %rd3, 3;
	add.s64 	%rd12, %rd2, %rd11;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd12];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs1;
	cvt.f32.f16 	%f29, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs2;
	cvt.f32.f16 	%f30, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs3;
	cvt.f32.f16 	%f31, %temp;
	}
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f32, %temp;
	}

BB0_4:
	shl.b32 	%r3, %r1, 2;
	setp.ge.s32	%p7, %r3, %r7;
	@%p7 bra 	BB0_8;

	mad.lo.s32 	%r18, %r2, %r5, %r3;
	cvt.s64.s32	%rd4, %r18;
	@%p6 bra 	BB0_7;

	shl.b64 	%rd13, %rd4, 4;
	add.s64 	%rd14, %rd1, %rd13;
	mov.f32 	%f21, 0f00000000;
	st.global.v4.f32 	[%rd14], {%f21, %f21, %f21, %f29};
	bra.uni 	BB0_8;

BB0_7:
	shl.b64 	%rd15, %rd4, 3;
	add.s64 	%rd16, %rd1, %rd15;
	mov.f32 	%f22, 0f00000000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f29;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f22;
	mov.b16 	%rs10, %temp;
}
	st.global.v4.u16 	[%rd16], {%rs10, %rs10, %rs10, %rs9};

BB0_8:
	add.s32 	%r19, %r3, 1;
	mad.lo.s32 	%r20, %r2, %r5, %r3;
	mul.wide.s32 	%rd17, %r20, 16;
	add.s64 	%rd5, %rd1, %rd17;
	mul.wide.s32 	%rd18, %r20, 8;
	add.s64 	%rd6, %rd1, %rd18;
	setp.ge.s32	%p9, %r19, %r7;
	@%p9 bra 	BB0_12;

	@%p6 bra 	BB0_11;

	mov.f32 	%f23, 0f00000000;
	st.global.v4.f32 	[%rd5+16], {%f23, %f23, %f23, %f30};
	bra.uni 	BB0_12;

BB0_11:
	mov.f32 	%f24, 0f00000000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f30;
	mov.b16 	%rs11, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f24;
	mov.b16 	%rs12, %temp;
}
	st.global.v4.u16 	[%rd6+8], {%rs12, %rs12, %rs12, %rs11};

BB0_12:
	add.s32 	%r21, %r3, 2;
	setp.ge.s32	%p11, %r21, %r7;
	@%p11 bra 	BB0_16;

	@%p6 bra 	BB0_15;

	mov.f32 	%f25, 0f00000000;
	st.global.v4.f32 	[%rd5+32], {%f25, %f25, %f25, %f31};
	bra.uni 	BB0_16;

BB0_15:
	mov.f32 	%f26, 0f00000000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f31;
	mov.b16 	%rs13, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f26;
	mov.b16 	%rs14, %temp;
}
	st.global.v4.u16 	[%rd6+16], {%rs14, %rs14, %rs14, %rs13};

BB0_16:
	add.s32 	%r22, %r3, 3;
	setp.ge.s32	%p13, %r22, %r7;
	@%p13 bra 	BB0_20;

	@%p6 bra 	BB0_19;

	mov.f32 	%f27, 0f00000000;
	st.global.v4.f32 	[%rd5+48], {%f27, %f27, %f27, %f32};
	bra.uni 	BB0_20;

BB0_19:
	mov.f32 	%f28, 0f00000000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f32;
	mov.b16 	%rs15, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f28;
	mov.b16 	%rs16, %temp;
}
	st.global.v4.u16 	[%rd6+24], {%rs16, %rs16, %rs16, %rs15};

BB0_20:
	ret;
}

.visible .entry CopyDeepAlphaKernel(
	.param .u64 CopyDeepAlphaKernel_param_0,
	.param .u32 CopyDeepAlphaKernel_param_1,
	.param .u32 CopyDeepAlphaKernel_param_2,
	.param .u32 CopyDeepAlphaKernel_param_3,
	.param .u64 CopyDeepAlphaKernel_param_4,
	.param .u32 CopyDeepAlphaKernel_param_5,
	.param .u32 CopyDeepAlphaKernel_param_6,
	.param .u32 CopyDeepAlphaKernel_param_7,
	.param .u32 CopyDeepAlphaKernel_param_8
)
{
	.reg .pred 	%p<9>;
	.reg .s16 	%rs<11>;
	.reg .s32 	%r<18>;
	.reg .f32 	%f<24>;
	.reg .s64 	%rd<15>;


	ld.param.u64 	%rd5, [CopyDeepAlphaKernel_param_0];
	ld.param.u32 	%r3, [CopyDeepAlphaKernel_param_1];
	ld.param.u32 	%r4, [CopyDeepAlphaKernel_param_2];
	ld.param.u32 	%r5, [CopyDeepAlphaKernel_param_3];
	ld.param.u64 	%rd6, [CopyDeepAlphaKernel_param_4];
	ld.param.u32 	%r6, [CopyDeepAlphaKernel_param_5];
	ld.param.u32 	%r7, [CopyDeepAlphaKernel_param_6];
	ld.param.u32 	%r8, [CopyDeepAlphaKernel_param_7];
	ld.param.u32 	%r9, [CopyDeepAlphaKernel_param_8];
	cvta.to.global.u64 	%rd1, %rd6;
	cvta.to.global.u64 	%rd2, %rd5;
	mov.u32 	%r10, %ntid.x;
	mov.u32 	%r11, %ctaid.x;
	mov.u32 	%r12, %tid.x;
	mad.lo.s32 	%r1, %r10, %r11, %r12;
	mov.u32 	%r13, %ntid.y;
	mov.u32 	%r14, %ctaid.y;
	mov.u32 	%r15, %tid.y;
	mad.lo.s32 	%r2, %r13, %r14, %r15;
	setp.lt.s32	%p1, %r1, %r8;
	setp.lt.s32	%p2, %r2, %r9;
	and.pred  	%p3, %p1, %p2;
	@!%p3 bra 	BB1_10;
	bra.uni 	BB1_1;

BB1_1:
	setp.lt.s32	%p4, %r1, %r4;
	setp.lt.s32	%p5, %r2, %r5;
	and.pred  	%p6, %p4, %p5;
	@%p6 bra 	BB1_3;

	mov.f32 	%f23, 0f00000000;
	bra.uni 	BB1_7;

BB1_3:
	setp.eq.s32	%p7, %r7, 0;
	mad.lo.s32 	%r16, %r2, %r3, %r1;
	cvt.s64.s32	%rd3, %r16;
	@%p7 bra 	BB1_5;

	shl.b64 	%rd7, %rd3, 4;
	add.s64 	%rd8, %rd2, %rd7;
	ld.global.v4.f32 	{%f16, %f17, %f18, %f19}, [%rd8];
	mov.f32 	%f22, %f19;
	mov.f32 	%f3, %f18;
	mov.f32 	%f2, %f17;
	mov.f32 	%f1, %f16;
	bra.uni 	BB1_6;

BB1_5:
	shl.b64 	%rd9, %rd3, 3;
	add.s64 	%rd10, %rd2, %rd9;
	ld.global.v4.u16 	{%rs1, %rs2, %rs3, %rs4}, [%rd10];
	{
	.reg .b16 %temp;
	mov.b16 	%temp, %rs4;
	cvt.f32.f16 	%f22, %temp;
	}

BB1_6:
	mov.f32 	%f23, %f22;

BB1_7:
	mad.lo.s32 	%r17, %r2, %r6, %r1;
	cvt.s64.s32	%rd4, %r17;
	setp.eq.s32	%p8, %r7, 0;
	@%p8 bra 	BB1_9;

	shl.b64 	%rd11, %rd4, 4;
	add.s64 	%rd12, %rd1, %rd11;
	mov.f32 	%f20, 0f00000000;
	st.global.v4.f32 	[%rd12], {%f20, %f20, %f20, %f23};
	bra.uni 	BB1_10;

BB1_9:
	shl.b64 	%rd13, %rd4, 3;
	add.s64 	%rd14, %rd1, %rd13;
	mov.f32 	%f21, 0f00000000;
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f23;
	mov.b16 	%rs9, %temp;
}
	{
	.reg .b16 %temp;
	cvt.rn.ftz.f16.f32 	%temp, %f21;
	mov.b16 	%rs10, %temp;
}
	st.global.v4.u16 	[%rd14], {%rs10, %rs10, %rs10, %rs9};

BB1_10:
	ret;
}


